Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22171

1

T3

19

T4

13

T5

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18825

1

T3

19

T4

13

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3346

1

T7

2

T10

2

T13

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16739

1

T3

19

T4

13

T5

11

auto[1]

5432

1

T10

6

T15

14

T16

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18427

1

T3

19

T4

13

T5

11

auto[1]

3744

1

T6

2

T7

1

T10

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	232	1			T16	4		T151	13		T50	22
values[0]	36	1			T186	1		T316	1		T324	1
values[1]	325	1			T10	3		T12	3		T177	11
values[2]	789	1			T15	14		T72	25		T187	6
values[3]	520	1			T10	4		T62	1		T68	2
values[4]	891	1			T59	23		T62	1		T104	10
values[5]	717	1			T7	2		T13	6		T14	5
values[6]	720	1			T72	14		T110	1		T140	35
values[7]	640	1			T18	19		T239	1		T42	12
values[8]	658	1			T10	2		T151	5		T40	1
values[9]	2849	1			T17	1		T58	3		T59	14
minimum	13794	1			T3	19		T4	13		T5	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	518	1			T10	3		T12	3		T15	2
values[1]	654	1			T10	4		T15	12		T187	6
values[2]	682	1			T59	23		T62	1		T68	2
values[3]	843	1			T62	1		T104	10		T177	25
values[4]	638	1			T7	2		T13	6		T14	5
values[5]	675	1			T72	14		T110	1		T140	35
values[6]	2873	1			T10	2		T17	1		T18	19
values[7]	650	1			T151	5		T140	10		T40	1
values[8]	651	1			T16	4		T58	3		T59	14
values[9]	104	1			T151	13		T249	16		T318	34
minimum	13883	1			T3	19		T4	13		T5	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

3772

1

T10

1

T13

2

T15

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T10	2		T12	2		T177	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T15	1		T72	14		T73	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	4		T170	13		T171	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T15	8		T187	1		T90	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T59	13		T156	10		T278	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T62	1		T68	2		T143	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T104	1		T177	11		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T62	1		T191	14		T197	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	5		T143	13		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	1		T13	5		T236	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T72	9		T140	18		T34	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T110	1		T245	1		T278	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1494	1			T17	1		T18	9		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T10	1		T154	11		T145	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T151	1		T140	3		T154	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T40	1		T240	1		T244	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T16	4		T58	3		T59	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T267	8		T155	10		T246	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T249	16		T318	13		T310	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T151	1		T322	6		T330	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13709	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T180	1		T261	1		T319	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T10	1		T12	1		T177	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T15	1		T72	11		T73	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T321	14		T298	5		T269	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T15	4		T187	5		T90	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T59	10		T156	9		T253	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T143	11		T238	6		T271	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T104	9		T177	14		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T197	9		T37	5		T42	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T143	9		T168	15		T144	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T7	1		T13	1		T197	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T72	5		T140	17		T145	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T245	11		T269	21		T284	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	941	1			T18	10		T60	8		T61	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	1		T154	10		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T151	4		T140	7		T154	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T240	9		T244	19		T218	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T59	2		T187	2		T70	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T248	5		T250	10		T254	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T318	21		T310	6		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T151	12		T322	8		T375	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T6	2		T10	3		T12	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T180	12		T261	2		T319	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T16	4		T50	11		T256	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T151	1		T254	10		T314	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T186	1		T316	1		T324	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T326	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T10	2		T12	2		T177	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T73	5		T24	3		T278	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T170	3		T46	1		T50	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T15	9		T72	14		T187	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T10	4		T170	10		T171	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T62	1		T68	2		T143	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T59	13		T104	1		T177	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T62	1		T191	14		T36	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T14	5		T143	13		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	1		T13	5		T236	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T72	9		T140	18		T34	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T110	1		T146	1		T148	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T18	9		T239	1		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T154	11		T145	4		T155	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T151	1		T154	3		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	1		T40	1		T244	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1577	1			T17	1		T58	3		T59	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T267	8		T240	1		T155	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13690	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T50	11		T376	1		T311	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T151	12		T254	11		T377	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T276	6		T325	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T326	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T10	1		T12	1		T177	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T73	1		T180	12		T281	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T50	7		T321	14		T298	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T15	5		T72	11		T187	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T253	12		T260	11		T378	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T143	11		T238	6		T271	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T59	10		T104	9		T177	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T37	5		T144	9		T182	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T143	9		T144	11		T145	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T7	1		T13	1		T197	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T72	5		T140	17		T168	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T146	11		T245	11		T318	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T18	10		T42	11		T277	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T154	10		T145	11		T254	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T151	4		T154	11		T148	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T10	1		T244	19		T218	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T59	2		T60	8		T61	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T240	9		T248	5		T250	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	2		T10	3		T12	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	2		T12	3		T177	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T15	2		T72	12		T73	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	4		T170	2		T171	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T15	5		T187	6		T90	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T59	11		T156	10		T278	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T62	1		T68	2		T143	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T104	10		T177	15		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T62	1		T191	1		T197	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T14	5		T143	10		T168	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T7	2		T13	4		T236	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T72	6		T140	18		T34	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T110	1		T245	12		T278	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T17	1		T18	11		T60	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T10	2		T154	11		T145	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T151	5		T140	8		T154	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T40	1		T240	10		T244	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T16	3		T58	2		T59	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T267	1		T155	1		T246	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T249	1		T318	22		T310	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T151	13		T322	9		T330	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13812	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T180	13		T261	3		T319	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T10	1		T191	9		T197	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T72	13		T73	1		T24	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T170	11		T242	14		T327	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T15	7		T156	23		T243	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T59	12		T156	9		T181	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T143	11		T36	8		T238	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T177	10		T270	6		T50	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T191	13		T197	9		T34	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T143	12		T328	2		T327	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T13	2		T178	14		T197	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T72	8		T140	17		T34	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T289	9		T192	9		T269	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1179	1			T18	8		T142	43		T188	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T154	10		T145	3		T155	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T140	2		T154	2		T164	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T244	7		T218	2		T277	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T16	1		T58	1		T59	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T267	7		T155	9		T248	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T249	15		T318	12		T310	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T322	5		T330	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T26	1		T325	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T322	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T16	3		T50	12		T256	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T151	13		T254	12		T314	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T186	1		T316	1		T324	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T326	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T10	2		T12	3		T177	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T73	5		T24	2		T278	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T170	1		T46	1		T50	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T15	7		T72	12		T187	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T10	4		T170	1		T171	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T62	1		T68	2		T143	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T59	11		T104	10		T177	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T62	1		T191	1		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T14	5		T143	10		T144	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	2		T13	4		T236	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T72	6		T140	18		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T110	1		T146	12		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T18	11		T239	1		T42	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T154	11		T145	12		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T151	5		T154	12		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	2		T40	1		T244	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T17	1		T58	2		T59	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T267	1		T240	10		T155	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13794	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T16	1		T50	10		T376	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T254	9		T377	2		T316	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T325	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T10	1		T191	9		T197	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T73	1		T24	1		T281	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T170	2		T50	8		T242	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T15	7		T72	13		T156	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T170	9		T181	13		T201	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T143	11		T238	5		T259	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T59	12		T177	10		T270	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T191	13		T36	8		T265	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T143	12		T145	7		T50	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	2		T178	14		T197	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T72	8		T140	17		T34	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T148	5		T27	1		T379	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T18	8		T277	6		T249	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T154	10		T145	3		T155	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T154	2		T148	8		T291	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T244	7		T218	2		T277	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T58	1		T59	11		T142	43
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T267	7		T155	9		T248	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

auto[0]

3772

1

T10

1

T13

2

T15

7