Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T273	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T274	1		T276	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T275	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T62	1		T177	11		T34	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T72	9		T140	18		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T141	9		T51	1		T179	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	4		T59	13		T177	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T187	1		T197	13		T36	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T197	10		T147	1		T155	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1485	1			T10	1		T17	1		T60	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T186	1		T239	1		T70	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T110	1		T170	10		T140	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T40	1		T144	1		T247	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T151	1		T170	3		T50	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T72	14		T267	8		T240	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	2		T62	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T10	2		T143	13		T191	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T104	1		T147	1		T256	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T14	5		T25	4		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T13	5		T16	4		T59	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T7	1		T15	9		T18	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13690	1			T3	19		T4	13		T5	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T276	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T177	14		T42	11		T154	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T72	5		T140	17		T144	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T141	8		T51	11		T180	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T59	10		T177	10		T37	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T187	2		T197	9		T267	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T197	9		T277	12		T183	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	882	1			T10	1		T60	8		T61	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T70	3		T168	15		T282	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T140	7		T244	19		T270	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T144	12		T218	1		T288	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T151	4		T50	14		T271	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T72	11		T240	9		T241	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T12	1		T151	12		T252	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	1		T143	9		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T104	9		T256	2		T246	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T25	2		T266	1		T156	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T13	1		T59	2		T73	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T7	1		T15	5		T18	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	2		T10	3		T12	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T62	1		T177	15		T34	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T59	11		T72	6		T140	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T197	10		T141	10		T51	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	4		T177	11		T37	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T187	3		T36	1		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T197	10		T147	1		T277	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1179	1			T17	1		T60	9		T61	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T186	1		T239	1		T70	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T10	2		T151	5		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T72	12		T40	1		T144	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T12	3		T62	1		T151	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T191	1		T240	10		T241	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T104	10		T148	1		T278	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T10	2		T143	10		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	4		T59	3		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T7	2		T14	5		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T16	3		T68	2		T236	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T15	5		T58	2		T62	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T197	10		T279	1		T280	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T18	11		T187	6		T237	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13794	1			T3	19		T4	13		T5	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T177	10		T34	14		T154	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T59	12		T72	8		T140	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T197	12		T141	7		T182	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T155	23		T289	11		T181	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T36	8		T164	1		T267	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T197	9		T277	6		T243	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1150	1			T142	43		T188	16		T290	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T70	3		T191	13		T24	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T170	2		T140	2		T244	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T72	13		T267	7		T50	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T242	14		T192	13		T283	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T191	9		T156	9		T289	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T148	5		T291	13		T27	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T10	1		T143	12		T25	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	2		T59	11		T178	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T266	1		T148	8		T156	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T16	1		T73	1		T50	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T15	7		T58	1		T143	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T197	2		T292	9		T285	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T18	8		T260	13		T293	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum , values[0]]	*	--	--	4
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T273	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T274	1		T276	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T275	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T62	1		T177	15		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T72	6		T140	18		T144	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T141	10		T51	12		T179	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	4		T59	11		T177	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T187	3		T197	10		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T197	10		T147	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1197	1			T10	2		T17	1		T60	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T186	1		T239	1		T70	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T110	1		T170	1		T140	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	1		T144	13		T247	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T151	5		T170	1		T50	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T72	12		T267	1		T240	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	3		T62	1		T151	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	2		T143	10		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T104	10		T147	1		T256	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T14	5		T25	5		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T13	4		T16	3		T59	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	402	1			T7	2		T15	7		T18	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13794	1			T3	19		T4	13		T5	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T177	10		T34	14		T154	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T72	8		T140	17		T53	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T141	7		T182	10		T215	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T59	12		T155	14		T277	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T197	12		T36	8		T164	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T197	9		T155	9		T277	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1170	1			T142	43		T188	16		T290	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T70	3		T191	13		T24	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T170	9		T140	2		T244	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T218	2		T288	3		T157	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T170	2		T50	13		T148	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T72	13		T267	7		T50	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T242	14		T192	13		T283	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	1		T143	12		T191	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T256	2		T254	7		T268	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T25	1		T266	1		T156	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T13	2		T16	1		T59	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T15	7		T18	8		T58	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

auto[0]

3772

1

T10

1

T13

2

T15

7