Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22171

1

T3

19

T4

13

T5

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19042

1

T3

19

T4

13

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3129

1

T10

2

T13

6

T15

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16698

1

T3

19

T4

13

T5

11

auto[1]

5473

1

T10

2

T12

3

T15

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18427

1

T3

19

T4

13

T5

11

auto[1]

3744

1

T6

2

T7

1

T10

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	55	1			T141	16		T251	3		T272	7
values[1]	650	1			T59	14		T104	10		T177	11
values[2]	581	1			T7	2		T15	12		T18	19
values[3]	784	1			T14	5		T58	3		T187	9
values[4]	571	1			T10	3		T186	1		T70	9
values[5]	2818	1			T17	1		T60	9		T61	7
values[6]	617	1			T12	3		T15	2		T62	1
values[7]	632	1			T59	23		T72	25		T73	6
values[8]	795	1			T10	4		T177	25		T236	1
values[9]	874	1			T10	2		T13	6		T16	4
minimum	13794	1			T3	19		T4	13		T5	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	759	1			T59	14		T104	10		T68	2
values[1]	735	1			T7	2		T15	12		T18	19
values[2]	725	1			T14	5		T187	9		T178	15
values[3]	2730	1			T10	3		T17	1		T60	9
values[4]	616	1			T62	2		T110	1		T143	23
values[5]	674	1			T12	3		T15	2		T59	23
values[6]	670	1			T10	4		T72	25		T236	1
values[7]	642	1			T16	4		T177	25		T239	1
values[8]	712	1			T10	2		T13	6		T72	14
values[9]	96	1			T155	10		T284	12		T294	5
minimum	13812	1			T3	19		T4	13		T5	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

3772

1

T10

1

T13

2

T15

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T59	12		T104	1		T68	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T151	1		T154	10		T141	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	1		T18	9		T34	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T15	8		T58	3		T62	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T14	5		T187	1		T178	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T187	1		T170	3		T197	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1506	1			T10	2		T17	1		T60	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T37	1		T256	3		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T62	1		T143	12		T70	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T62	1		T110	1		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	2		T15	1		T154	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T59	13		T140	3		T34	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T10	4		T72	14		T236	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T73	5		T144	1		T267	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T16	4		T151	1		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T177	11		T239	1		T170	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T72	9		T143	13		T191	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T10	1		T13	5		T50	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T294	1		T56	1		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T155	10		T284	1		T296	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13698	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T297	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T59	2		T104	9		T177	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T151	12		T154	8		T141	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	1		T18	10		T42	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	4		T39	1		T168	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T187	2		T140	17		T145	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T187	5		T197	9		T298	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	902	1			T10	1		T60	8		T61	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T37	5		T256	2		T246	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T143	11		T70	3		T197	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T51	11		T266	1		T182	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	1		T15	1		T154	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T59	10		T140	7		T50	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T72	11		T244	19		T254	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T73	1		T144	12		T267	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T151	4		T42	11		T25	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T177	14		T144	9		T145	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T72	5		T143	9		T144	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T10	1		T13	1		T50	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T294	4		T56	1		T299	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T284	11		T296	16		T300	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T6	2		T10	3		T12	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T297	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T272	5		T301	1		T302	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T141	8		T251	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T59	12		T104	1		T177	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T151	1		T154	10		T245	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	1		T18	9		T68	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T15	8		T62	1		T197	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T14	5		T187	1		T178	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T58	3		T187	1		T170	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T10	2		T186	1		T70	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T37	1		T164	2		T246	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1570	1			T17	1		T60	1		T61	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T62	1		T110	1		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	2		T15	1		T62	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T34	15		T267	8		T50	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T72	14		T237	1		T244	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T59	13		T73	5		T140	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	4		T236	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T177	11		T239	1		T170	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T16	4		T72	9		T143	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	1		T13	5		T50	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13690	1			T3	19		T4	13		T5	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T272	2		T301	11		T303	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T141	8		T251	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T59	2		T104	9		T177	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T151	12		T154	8		T245	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	1		T18	10		T42	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T15	4		T197	9		T168	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T187	2		T145	9		T90	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T187	5		T39	1		T298	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T10	1		T70	3		T140	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T37	5		T246	1		T250	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	981	1			T60	8		T61	6		T111	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T51	11		T256	2		T266	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T12	1		T15	1		T154	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T50	14		T271	5		T304	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T72	11		T244	19		T254	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T59	10		T73	1		T140	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T151	4		T42	11		T25	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T177	14		T144	9		T267	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T72	5		T143	9		T144	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T10	1		T13	1		T50	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	2		T10	3		T12	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T59	3		T104	10		T68	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T151	13		T154	9		T141	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	2		T18	11		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T15	5		T58	2		T62	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T14	5		T187	3		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T187	6		T170	1		T197	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T10	2		T17	1		T60	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T37	6		T256	3		T246	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T62	1		T143	12		T70	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T62	1		T110	1		T51	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	3		T15	2		T154	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T59	11		T140	8		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T10	4		T72	12		T236	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T73	5		T144	13		T267	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T16	3		T151	5		T42	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T177	15		T239	1		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T72	6		T143	10		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	2		T13	4		T50	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T294	5		T56	2		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T155	1		T284	12		T296	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13802	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T297	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T59	11		T197	9		T289	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T154	9		T141	7		T288	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T18	8		T34	3		T154	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T15	7		T58	1		T26	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T178	14		T140	17		T145	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T170	2		T197	12		T36	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1190	1			T10	1		T142	43		T188	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T256	2		T268	9		T291	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T143	11		T70	3		T191	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T266	1		T182	10		T249	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T154	10		T257	3		T305	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T59	12		T140	2		T34	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T72	13		T244	7		T254	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T73	1		T267	7		T148	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T16	1		T25	1		T50	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T177	10		T170	9		T145	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T72	8		T143	12		T191	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T13	2		T50	8		T281	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T306	1		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T155	9		T300	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T263	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T272	3		T301	12		T302	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T141	9		T251	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T59	3		T104	10		T177	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T151	13		T154	9		T245	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	2		T18	11		T68	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T15	5		T62	1		T197	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T14	5		T187	3		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T58	2		T187	6		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T10	2		T186	1		T70	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T37	6		T164	1		T246	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T17	1		T60	9		T61	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T62	1		T110	1		T51	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	3		T15	2		T62	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T34	1		T267	1		T50	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T72	12		T237	1		T244	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T59	11		T73	5		T140	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	4		T236	1		T151	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T177	15		T239	1		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T16	3		T72	6		T143	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	2		T13	4		T50	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13794	1			T3	19		T4	13		T5	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T272	4		T302	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T141	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T59	11		T197	9		T289	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T154	9		T288	4		T157	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T18	8		T34	3		T154	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T15	7		T197	12		T243	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T178	14		T145	7		T148	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T58	1		T170	2		T36	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T10	1		T70	3		T140	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T164	1		T250	11		T288	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T142	43		T188	16		T143	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T256	2		T266	1		T268	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T154	10		T218	2		T183	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T34	14		T267	7		T50	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T72	13		T244	7		T254	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T59	12		T73	1		T140	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T25	1		T50	10		T277	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T177	10		T170	9		T267	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T16	1		T72	8		T143	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	2		T50	8		T155	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

auto[0]

3772

1

T10

1

T13

2

T15

7