Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22171

1

T3

19

T4

13

T5

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18851

1

T3

19

T4

13

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3320

1

T7

2

T10

7

T14

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16759

1

T3

19

T4

13

T5

11

auto[1]

5412

1

T10

2

T12

3

T15

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18427

1

T3

19

T4

13

T5

11

auto[1]

3744

1

T6

2

T7

1

T10

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	244	1			T15	12		T187	6		T73	6
values[0]	6	1			T298	6		-	-		-	-
values[1]	655	1			T62	1		T72	14		T177	25
values[2]	561	1			T10	4		T59	23		T177	11
values[3]	654	1			T187	3		T197	19		T164	2
values[4]	2627	1			T10	2		T17	1		T60	9
values[5]	523	1			T110	1		T186	1		T170	13
values[6]	846	1			T72	25		T151	5		T267	8
values[7]	709	1			T10	3		T12	3		T62	1
values[8]	600	1			T14	5		T104	10		T147	1
values[9]	952	1			T7	2		T13	6		T15	2
minimum	13794	1			T3	19		T4	13		T5	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	566	1			T59	23		T72	14		T177	25
values[1]	604	1			T10	4		T177	11		T197	22
values[2]	678	1			T187	3		T197	19		T36	9
values[3]	2590	1			T17	1		T60	9		T61	7
values[4]	686	1			T10	2		T72	25		T151	5
values[5]	787	1			T12	3		T62	1		T151	13
values[6]	593	1			T10	3		T104	10		T143	22
values[7]	633	1			T7	2		T13	6		T14	5
values[8]	922	1			T15	12		T16	4		T18	19
values[9]	118	1			T187	6		T197	12		T307	4
minimum	13994	1			T3	19		T4	13		T5	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

3772

1

T10

1

T13

2

T15

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T177	11		T154	10		T238	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T59	13		T72	9		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T197	13		T141	9		T51	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	4		T177	1		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T36	9		T164	2		T267	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T187	1		T197	10		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1484	1			T17	1		T60	1		T61	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T186	1		T239	1		T70	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T10	1		T151	1		T170	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T72	14		T40	1		T50	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	2		T62	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T191	10		T267	8		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T104	1		T242	15		T278	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T10	2		T143	13		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	5		T59	12		T34	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	1		T14	5		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T16	4		T68	2		T236	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T15	8		T18	9		T58	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T197	3		T280	1		T292	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T187	1		T307	1		T308	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13741	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T140	18		T53	3		T298	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T177	14		T154	8		T238	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T59	10		T72	5		T144	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T197	9		T141	8		T51	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T177	10		T37	5		T281	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T267	6		T145	11		T288	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T187	2		T197	9		T277	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	860	1			T60	8		T61	6		T111	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T70	3		T168	15		T144	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	1		T151	4		T140	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T72	11		T50	11		T218	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	1		T151	12		T283	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T240	9		T241	13		T90	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T104	9		T252	3		T284	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	1		T143	9		T39	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T13	1		T59	2		T256	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	1		T15	1		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T73	1		T42	2		T146	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T15	4		T18	10		T143	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T197	9		T309	10		T310	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T187	5		T307	3		T311	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	2		T10	3		T12	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T140	17		T53	1		T298	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T73	5		T197	3		T312	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T15	8		T187	1		T237	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T298	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T62	1		T177	11		T34	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T72	9		T140	18		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T197	13		T141	9		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	4		T59	13		T177	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T164	2		T267	8		T145	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T187	1		T197	10		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1481	1			T10	1		T17	1		T60	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T239	1		T70	6		T191	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T110	1		T170	13		T140	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T186	1		T40	1		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T151	1		T50	14		T271	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T72	14		T267	8		T240	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	2		T62	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T10	2		T143	13		T191	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T104	1		T147	1		T256	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	5		T46	1		T266	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	5		T16	4		T59	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T7	1		T15	1		T18	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13690	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T73	1		T197	9		T309	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T15	4		T187	5		T113	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T298	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T177	14		T42	11		T154	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T72	5		T140	17		T144	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T197	9		T141	8		T51	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T59	10		T177	10		T37	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T267	6		T145	11		T288	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T187	2		T197	9		T277	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	882	1			T10	1		T60	8		T61	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T70	3		T168	15		T282	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T140	7		T244	19		T270	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T144	12		T218	1		T288	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T151	4		T50	14		T271	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T72	11		T240	9		T241	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	1		T151	12		T252	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	1		T143	9		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T104	9		T256	2		T246	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T266	1		T156	23		T313	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	1		T59	2		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T7	1		T15	1		T18	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	2		T10	3		T12	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T177	15		T154	9		T238	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T59	11		T72	6		T144	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T197	10		T141	10		T51	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T10	4		T177	11		T37	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T36	1		T164	1		T267	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T187	3		T197	10		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1180	1			T17	1		T60	9		T61	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T186	1		T239	1		T70	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T10	2		T151	5		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T72	12		T40	1		T50	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	3		T62	1		T151	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T191	1		T267	1		T240	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T104	10		T242	1		T278	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	2		T143	10		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	4		T59	3		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T7	2		T14	5		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T16	3		T68	2		T236	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T15	5		T18	11		T58	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T197	10		T280	1		T292	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T187	6		T307	4		T308	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13835	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T140	18		T53	3		T298	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T177	10		T154	9		T238	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T59	12		T72	8		T277	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T197	12		T141	7		T182	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T155	23		T289	11		T181	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T36	8		T164	1		T267	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T197	9		T277	6		T243	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1164	1			T142	43		T188	16		T290	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T70	3		T191	13		T24	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T170	2		T140	2		T244	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T72	13		T50	10		T218	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T148	5		T192	13		T283	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T191	9		T267	7		T156	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T242	14		T291	13		T161	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T10	1		T143	12		T25	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T13	2		T59	11		T34	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T266	1		T148	8		T156	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T16	1		T178	14		T73	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T15	7		T18	8		T58	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T197	2		T292	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T293	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T34	14		T249	15		T213	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T140	17		T53	1		T195	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T73	5		T197	10		T312	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T15	5		T187	6		T237	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T298	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T62	1		T177	15		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T72	6		T140	18		T144	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T197	10		T141	10		T51	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T10	4		T59	11		T177	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T164	1		T267	7		T145	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T187	3		T197	10		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T10	2		T17	1		T60	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T239	1		T70	6		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T110	1		T170	2		T140	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T186	1		T40	1		T144	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T151	5		T50	15		T271	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T72	12		T267	1		T240	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	3		T62	1		T151	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	2		T143	10		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T104	10		T147	1		T256	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	5		T46	1		T266	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	4		T16	3		T59	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T7	2		T15	2		T18	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13794	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T73	1		T197	2		T292	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T15	7		T272	2		T300	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T177	10		T34	14		T154	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T72	8		T140	17		T53	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T197	12		T141	7		T182	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T59	12		T155	23		T277	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T164	1		T267	7		T145	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T197	9		T277	6		T181	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1167	1			T142	43		T188	16		T290	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T70	3		T191	13		T24	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T170	11		T140	2		T244	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T218	2		T288	3		T305	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T50	13		T271	13		T157	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T72	13		T267	7		T50	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T148	5		T242	14		T192	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T10	1		T143	12		T191	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T256	2		T254	7		T268	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T266	1		T156	23		T26	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	2		T16	1		T59	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T18	8		T58	1		T143	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

auto[0]

3772

1

T10

1

T13

2

T15

7