Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22171

1

T3

19

T4

13

T5

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18796

1

T3

19

T4

13

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3375

1

T7

2

T10

6

T13

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16734

1

T3

19

T4

13

T5

11

auto[1]

5437

1

T10

6

T15

14

T17

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18427

1

T3

19

T4

13

T5

11

auto[1]

3744

1

T6

2

T7

1

T10

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	18	1			T249	16		T314	1		T315	1
values[0]	40	1			T186	1		T24	3		T316	1
values[1]	289	1			T10	3		T12	3		T177	11
values[2]	829	1			T15	14		T72	25		T187	6
values[3]	516	1			T10	4		T62	1		T68	2
values[4]	889	1			T7	2		T59	23		T62	1
values[5]	750	1			T13	6		T14	5		T236	1
values[6]	691	1			T18	19		T72	14		T110	1
values[7]	666	1			T239	1		T40	1		T42	12
values[8]	663	1			T10	2		T151	5		T154	14
values[9]	3026	1			T16	4		T17	1		T58	3
minimum	13794	1			T3	19		T4	13		T5	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	583	1			T10	3		T12	3		T15	2
values[1]	661	1			T10	4		T15	12		T68	2
values[2]	666	1			T59	23		T62	1		T143	23
values[3]	832	1			T62	1		T104	10		T177	25
values[4]	741	1			T7	2		T13	6		T14	5
values[5]	636	1			T72	14		T110	1		T140	35
values[6]	2835	1			T10	2		T17	1		T18	19
values[7]	618	1			T239	1		T151	5		T140	10
values[8]	559	1			T16	4		T58	3		T59	14
values[9]	233	1			T151	13		T246	1		T317	1
minimum	13807	1			T3	19		T4	13		T5	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

3772

1

T10

1

T13

2

T15

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T10	2		T12	2		T177	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T15	1		T73	5		T24	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T170	13		T171	1		T242	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	4		T15	8		T68	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T59	13		T156	10		T278	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T62	1		T143	12		T36	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T143	13		T42	1		T144	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T62	1		T104	1		T177	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	5		T168	1		T237	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	1		T13	5		T236	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T72	9		T140	18		T34	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T110	1		T245	1		T278	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1493	1			T17	1		T18	9		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T10	1		T154	11		T145	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T239	1		T151	1		T140	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T40	1		T240	1		T244	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T16	4		T58	3		T59	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T70	6		T39	1		T267	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T254	18		T249	16		T318	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T151	1		T246	1		T317	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13691	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T319	1		T320	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T10	1		T12	1		T177	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T15	1		T73	1		T180	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T321	14		T298	5		T113	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	4		T72	11		T187	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T59	10		T156	9		T253	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T143	11		T238	6		T271	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T143	9		T42	2		T144	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T104	9		T177	14		T37	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T168	15		T145	9		T241	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	1		T13	1		T197	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T72	5		T140	17		T25	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T245	11		T269	21		T272	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	947	1			T18	10		T60	8		T61	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	1		T154	10		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T151	4		T140	7		T154	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T240	9		T244	19		T218	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T59	2		T187	2		T267	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T70	3		T39	1		T217	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T254	16		T318	21		T322	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T151	12		T254	11		T284	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T6	2		T10	3		T12	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T319	7		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T249	16		T315	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T314	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T186	1		T316	1		T323	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T24	3		T324	1		T276	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T10	2		T12	2		T177	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T73	5		T278	1		T180	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T46	1		T50	9		T242	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T15	9		T72	14		T187	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T170	13		T171	1		T278	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	4		T62	1		T68	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T59	13		T144	1		T270	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T7	1		T62	1		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	5		T143	13		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	5		T236	1		T197	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T18	9		T72	9		T140	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T110	1		T145	4		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T239	1		T42	1		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T40	1		T154	11		T155	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T151	1		T154	3		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	1		T244	8		T238	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T16	4		T17	1		T58	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T70	6		T151	1		T39	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13690	1			T3	19		T4	13		T5	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T325	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T276	6		T326	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T10	1		T12	1		T177	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T73	1		T180	12		T261	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T50	7		T321	14		T298	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T15	5		T72	11		T187	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T253	12		T260	11		T296	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T143	11		T238	6		T271	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T59	10		T144	12		T270	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T7	1		T104	9		T177	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T143	9		T42	2		T144	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	1		T197	18		T141	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T18	10		T72	5		T140	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T145	11		T146	11		T245	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T42	11		T51	11		T277	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T154	10		T254	7		T288	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T151	4		T154	11		T148	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	1		T244	19		T248	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T59	2		T60	8		T61	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T70	3		T151	12		T39	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	2		T10	3		T12	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T10	2		T12	3		T177	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T15	2		T73	5		T24	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T170	2		T171	1		T242	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T10	4		T15	5		T68	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T59	11		T156	10		T278	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T62	1		T143	12		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T143	10		T42	3		T144	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T62	1		T104	10		T177	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T14	5		T168	16		T237	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T7	2		T13	4		T236	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T72	6		T140	18		T34	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T110	1		T245	12		T278	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T17	1		T18	11		T60	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	2		T154	11		T145	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T239	1		T151	5		T140	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	1		T240	10		T244	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T16	3		T58	2		T59	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T70	6		T39	2		T267	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T254	17		T249	1		T318	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T151	13		T246	1		T317	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13798	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T319	8		T320	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T10	1		T191	9		T197	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T73	1		T24	1		T281	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T170	11		T242	14		T327	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	7		T72	13		T156	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T59	12		T156	9		T264	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T143	11		T36	8		T238	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T143	12		T270	6		T50	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T177	10		T191	13		T34	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T145	7		T328	2		T159	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	2		T178	14		T197	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T72	8		T140	17		T34	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T289	9		T192	9		T269	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1180	1			T18	8		T142	43		T188	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T154	10		T145	3		T155	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T140	2		T154	2		T164	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T244	7		T218	2		T277	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T16	1		T58	1		T59	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T70	3		T267	7		T155	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T254	17		T249	15		T318	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T254	9		T329	10		T330	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T249	1		T315	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T314	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T186	1		T316	1		T323	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T24	2		T324	1		T276	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T10	2		T12	3		T177	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T73	5		T278	1		T180	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T46	1		T50	8		T242	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T15	7		T72	12		T187	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T170	2		T171	1		T278	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	4		T62	1		T68	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T59	11		T144	13		T270	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T7	2		T62	1		T104	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T14	5		T143	10		T42	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	4		T236	1		T197	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T18	11		T72	6		T140	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T110	1		T145	12		T146	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T239	1		T42	12		T51	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T40	1		T154	11		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T151	5		T154	12		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	2		T244	20		T238	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T16	3		T17	1		T58	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T70	6		T151	13		T39	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13794	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T249	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T325	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T24	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T10	1		T191	9		T197	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T73	1		T331	9		T196	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T50	8		T242	14		T327	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T15	7		T72	13		T156	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T170	11		T201	9		T260	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T143	11		T238	5		T259	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T59	12		T270	6		T53	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T177	10		T178	14		T191	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T143	12		T145	7		T50	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	2		T197	21		T34	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T18	8		T72	8		T140	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T145	3		T194	6		T332	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T277	6		T249	8		T304	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T154	10		T155	14		T254	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T154	2		T148	8		T291	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T244	7		T248	5		T277	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T16	1		T58	1		T59	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T70	3		T267	7		T155	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

auto[0]

3772

1

T10

1

T13

2

T15

7