Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22171

1

T3

19

T4

13

T5

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17017

1

T3

19

T4

13

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

5154

1

T10

5

T14

5

T15

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16886

1

T3

19

T4

13

T5

11

auto[1]

5285

1

T7

2

T10

5

T12

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18427

1

T3

19

T4

13

T5

11

auto[1]

3744

1

T6

2

T7

1

T10

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T183	1		T320	1		T316	10
values[0]	34	1			T333	8		T334	19		T335	1
values[1]	698	1			T12	3		T186	1		T187	6
values[2]	833	1			T187	3		T151	13		T197	19
values[3]	610	1			T59	23		T72	25		T178	15
values[4]	562	1			T170	3		T197	12		T34	4
values[5]	722	1			T15	12		T18	19		T72	14
values[6]	602	1			T10	3		T16	4		T110	1
values[7]	654	1			T7	2		T62	1		T104	10
values[8]	606	1			T13	6		T14	5		T58	3
values[9]	3044	1			T10	6		T15	2		T17	1
minimum	13794	1			T3	19		T4	13		T5	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	945	1			T12	3		T186	1		T187	9
values[1]	2890	1			T17	1		T60	9		T61	7
values[2]	577	1			T59	23		T72	25		T178	15
values[3]	620	1			T72	14		T177	11		T34	4
values[4]	744	1			T18	19		T177	25		T143	22
values[5]	618	1			T10	3		T15	12		T16	4
values[6]	534	1			T7	2		T104	10		T151	5
values[7]	628	1			T10	4		T13	6		T14	5
values[8]	617	1			T10	2		T15	2		T59	14
values[9]	184	1			T46	1		T246	2		T317	1
minimum	13814	1			T3	19		T4	13		T5	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

3772

1

T10

1

T13

2

T15

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T12	2		T186	1		T187	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T151	1		T171	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T197	10		T24	3		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1457	1			T17	1		T60	1		T61	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T170	3		T140	3		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T59	13		T72	14		T178	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T72	9		T168	1		T298	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T177	1		T34	4		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T18	9		T143	13		T191	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T177	11		T197	13		T36	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T62	1		T110	1		T271	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	2		T15	8		T16	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	1		T104	1		T170	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T151	1		T267	8		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	4		T13	5		T62	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	5		T58	3		T62	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T15	1		T70	6		T145	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	1		T59	12		T68	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T312	1		T268	3		T304	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T46	1		T246	1		T317	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13692	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T191	14		T336	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T12	1		T187	7		T244	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T151	12		T144	11		T50	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T197	9		T256	2		T321	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	896	1			T60	8		T61	6		T111	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T140	7		T50	14		T321	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T59	10		T72	11		T197	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T72	5		T168	15		T298	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T177	10		T42	11		T53	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T18	10		T143	9		T144	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T177	14		T197	9		T154	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T271	5		T156	9		T250	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	1		T15	4		T37	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	1		T104	9		T140	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T151	4		T267	6		T145	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	1		T73	1		T248	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T143	11		T270	2		T148	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T15	1		T70	3		T145	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T10	1		T59	2		T241	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T304	1		T258	4		T337	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T246	1		T288	3		T183	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	2		T10	3		T12	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T183	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T320	1		T316	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T334	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T333	8		T335	1		T338	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	2		T186	1		T187	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T191	14		T171	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T187	1		T197	10		T24	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T151	1		T25	4		T50	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T140	3		T46	1		T50	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T59	13		T72	14		T178	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T170	3		T168	1		T339	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T197	3		T34	4		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T18	9		T72	9		T143	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T15	8		T177	12		T197	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T110	1		T191	10		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	2		T16	4		T36	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	1		T62	1		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T151	1		T37	1		T154	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	5		T239	1		T170	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	5		T58	3		T62	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T10	4		T15	1		T62	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1632	1			T10	1		T17	1		T59	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13690	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T316	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T334	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	1		T187	5		T50	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T144	11		T254	7		T182	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T187	2		T197	9		T244	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T151	12		T25	2		T50	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T140	7		T50	14		T321	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T59	10		T72	11		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T168	15		T288	6		T281	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T197	9		T42	11		T159	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T18	10		T72	5		T143	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T15	4		T177	24		T197	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T240	9		T271	5		T156	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T10	1		T158	12		T265	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	1		T104	9		T73	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T151	4		T37	5		T154	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	1		T154	8		T248	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T143	11		T270	2		T253	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	1		T70	3		T145	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1040	1			T10	1		T59	2		T60	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	2		T10	3		T12	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T12	3		T186	1		T187	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T151	13		T171	1		T144	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T197	10		T24	2		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1210	1			T17	1		T60	9		T61	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T170	1		T140	8		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T59	11		T72	12		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T72	6		T168	16		T298	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T177	11		T34	1		T42	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T18	11		T143	10		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T177	15		T197	10		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T62	1		T110	1		T271	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T10	2		T15	5		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	2		T104	10		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T151	5		T267	7		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	4		T13	4		T62	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	5		T58	2		T62	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T15	2		T70	6		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	2		T59	3		T68	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T312	1		T268	1		T304	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T46	1		T246	2		T317	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13797	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T191	1		T336	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T244	7		T50	10		T155	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T50	8		T254	7		T182	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T197	9		T24	1		T256	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1143	1			T142	43		T188	16		T290	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T170	2		T140	2		T50	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T59	12		T72	13		T178	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T72	8		T288	2		T289	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T34	3		T53	1		T340	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T18	8		T143	12		T191	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T177	10		T197	12		T36	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T271	13		T156	9		T289	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	1		T15	7		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T170	9		T140	17		T34	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T267	7		T145	7		T238	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T13	2		T73	1		T148	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T58	1		T143	11		T270	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T70	3		T145	3		T266	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T59	11		T250	11		T264	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T268	2		T276	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T288	3		T183	7		T159	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T191	13		T336	2		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T183	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T320	1		T316	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T334	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T333	1		T335	1		T338	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T12	3		T186	1		T187	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T191	1		T171	1		T144	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T187	3		T197	10		T24	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T151	13		T25	5		T50	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T140	8		T46	1		T50	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T59	11		T72	12		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T170	1		T168	16		T339	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T197	10		T34	1		T42	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T18	11		T72	6		T143	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T15	5		T177	26		T197	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T110	1		T191	1		T240	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T10	2		T16	3		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T7	2		T62	1		T104	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T151	5		T37	6		T154	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	4		T239	1		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	5		T58	2		T62	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T10	4		T15	2		T62	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1382	1			T10	2		T17	1		T59	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13794	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T316	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T334	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T333	7		T338	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T50	10		T156	23		T254	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T191	13		T254	7		T182	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T197	9		T24	1		T244	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T25	1		T50	8		T277	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T140	2		T50	13		T262	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T59	12		T72	13		T178	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T170	2		T288	2		T289	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T197	2		T34	3		T259	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T18	8		T72	8		T143	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T15	7		T177	10		T197	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T191	9		T271	13		T156	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T10	1		T16	1		T36	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T73	1		T140	17		T34	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T154	2		T267	7		T145	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	2		T170	9		T154	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T58	1		T143	11		T270	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T70	3		T145	3		T266	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1290	1			T59	11		T142	43		T188	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

auto[0]

3772

1

T10

1

T13

2

T15

7