Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22171

1

T3

19

T4

13

T5

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18933

1

T3

19

T4

13

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3238

1

T10

6

T12

3

T13

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16382

1

T3

19

T4

13

T5

11

auto[1]

5789

1

T6

3

T10

3

T12

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18427

1

T3

19

T4

13

T5

11

auto[1]

3744

1

T6

2

T7

1

T10

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	290	1			T6	3		T12	2		T13	2
values[0]	46	1			T217	3		T198	13		T295	1
values[1]	862	1			T15	14		T58	3		T62	1
values[2]	2913	1			T10	4		T16	4		T17	1
values[3]	577	1			T10	3		T14	5		T36	9
values[4]	545	1			T62	1		T72	25		T151	13
values[5]	604	1			T12	3		T13	6		T62	1
values[6]	641	1			T59	23		T236	1		T151	5
values[7]	400	1			T7	2		T59	14		T239	1
values[8]	643	1			T170	10		T154	21		T145	15
values[9]	1129	1			T10	2		T18	19		T177	25
minimum	13521	1			T3	19		T4	13		T5	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1141	1			T15	14		T58	3		T62	1
values[1]	2825	1			T10	4		T16	4		T17	1
values[2]	548	1			T10	3		T14	5		T62	1
values[3]	589	1			T13	6		T186	1		T151	13
values[4]	597	1			T12	3		T72	14		T236	1
values[5]	605	1			T59	23		T62	1		T73	6
values[6]	441	1			T7	2		T59	14		T239	1
values[7]	701	1			T18	19		T197	22		T24	3
values[8]	747	1			T10	2		T177	25		T187	6
values[9]	179	1			T70	9		T140	10		T240	10
minimum	13798	1			T3	19		T4	13		T5	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

3772

1

T10

1

T13

2

T15

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T15	1		T104	1		T68	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T15	8		T58	3		T62	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T16	4		T17	1		T60	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	4		T110	1		T178	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	2		T14	5		T62	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T72	14		T321	1		T288	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T151	1		T26	2		T278	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	5		T186	1		T164	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T236	1		T191	24		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	2		T72	9		T34	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T59	13		T62	1		T73	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T151	1		T34	15		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	1		T59	12		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T239	1		T270	7		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T24	3		T37	1		T244	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T18	9		T197	13		T154	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T177	11		T170	3		T197	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	1		T187	1		T170	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T70	6		T240	1		T201	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T140	3		T50	9		T159	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13690	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T341	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T15	1		T104	9		T177	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T15	4		T143	11		T241	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	938	1			T60	8		T61	6		T111	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T90	1		T254	11		T180	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T10	1		T145	9		T117	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T72	11		T321	14		T288	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T151	12		T342	1		T113	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	1		T53	1		T256	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T168	15		T144	11		T321	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	1		T72	5		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T59	10		T73	1		T197	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T151	4		T42	11		T156	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T7	1		T59	2		T146	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T270	2		T51	11		T246	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T37	5		T244	19		T266	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T18	10		T197	9		T154	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T177	14		T197	9		T154	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	1		T187	5		T140	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T70	3		T240	9		T316	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T140	7		T50	7		T159	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	2		T10	3		T12	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T341	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T6	3		T12	2		T13	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T193	1		T343	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T217	2		T198	1		T344	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T295	1		T345	1		T346	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T15	1		T104	1		T68	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T15	8		T58	3		T62	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T16	4		T17	1		T60	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T10	4		T110	1		T178	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T10	2		T14	5		T36	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T321	1		T90	2		T347	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T62	1		T151	1		T145	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T72	14		T164	2		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T62	1		T191	24		T197	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	2		T13	5		T72	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T59	13		T236	1		T154	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T151	1		T141	8		T46	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	1		T59	12		T73	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T239	1		T42	1		T247	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T266	3		T271	14		T288	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T170	10		T154	11		T145	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T177	11		T70	6		T170	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T10	1		T18	9		T187	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13417	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T343	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T217	1		T198	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T345	12		T346	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T15	1		T104	9		T238	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T15	4		T143	11		T241	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T60	8		T61	6		T111	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T254	11		T180	12		T262	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T10	1		T39	1		T250	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T321	14		T90	1		T304	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T151	12		T145	9		T342	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T72	11		T53	1		T256	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T197	9		T144	11		T321	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T12	1		T13	1		T72	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T59	10		T154	8		T168	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T151	4		T141	8		T156	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T7	1		T59	2		T73	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T42	11		T284	11		T348	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T266	1		T271	5		T288	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T154	10		T145	11		T270	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T177	14		T70	3		T197	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T10	1		T18	10		T187	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	2		T10	3		T12	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	377	1			T15	2		T104	10		T68	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T15	5		T58	2		T62	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T16	3		T17	1		T60	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T10	4		T110	1		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T10	2		T14	5		T62	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T72	12		T321	15		T288	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T151	13		T26	1		T278	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T13	4		T186	1		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T236	1		T191	2		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	3		T72	6		T34	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T59	11		T62	1		T73	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T151	5		T34	1		T42	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T7	2		T59	3		T146	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T239	1		T270	3		T51	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T24	2		T37	6		T244	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T18	11		T197	10		T154	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T177	15		T170	1		T197	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T10	2		T187	6		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T70	6		T240	10		T201	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T140	8		T50	8		T159	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13794	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T341	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T238	5		T155	14		T182	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T15	7		T58	1		T143	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T16	1		T142	43		T188	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T178	14		T254	9		T281	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T10	1		T36	8		T145	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T72	13		T288	3		T327	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T26	1		T289	11		T336	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	2		T164	1		T53	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T191	22		T248	5		T218	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T72	8		T34	3		T141	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T59	12		T73	1		T197	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T34	14		T156	23		T254	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T59	11		T305	10		T332	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T270	6		T156	9		T192	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T24	1		T244	7		T266	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T18	8		T197	12		T154	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T177	10		T170	2		T197	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T170	9		T140	17		T267	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T70	3		T201	9		T316	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T140	2		T50	8		T159	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T341	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T6	3		T12	2		T13	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T193	1		T343	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T217	3		T198	13		T344	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T295	1		T345	13		T346	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T15	2		T104	10		T68	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T15	5		T58	2		T62	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T16	3		T17	1		T60	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T10	4		T110	1		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	2		T14	5		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T321	15		T90	3		T347	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T62	1		T151	13		T145	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T72	12		T164	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T62	1		T191	2		T197	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	3		T13	4		T72	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T59	11		T236	1		T154	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T151	5		T141	9		T46	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T7	2		T59	3		T73	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T239	1		T42	12		T247	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T266	3		T271	6		T288	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T170	1		T154	11		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T177	15		T70	6		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T10	2		T18	11		T187	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13521	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T343	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T346	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T238	5		T155	14		T262	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T15	7		T58	1		T143	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T16	1		T142	43		T188	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T178	14		T242	14		T254	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	1		T36	8		T148	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T304	11		T118	11		T263	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T145	7		T117	9		T336	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T72	13		T164	1		T53	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T191	22		T197	9		T248	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T13	2		T72	8		T34	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T59	12		T154	9		T25	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T141	7		T156	23		T254	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T59	11		T73	1		T24	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T243	7		T192	9		T161	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T266	1		T271	13		T288	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T170	9		T154	10		T145	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T177	10		T70	3		T170	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T18	8		T140	19		T197	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

auto[0]

3772

1

T10

1

T13

2

T15

7