Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22171

1

T3

19

T4

13

T5

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19115

1

T3

19

T4

13

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3056

1

T10

6

T12

3

T13

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16646

1

T3

19

T4

13

T5

11

auto[1]

5525

1

T7

2

T10

6

T12

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18427

1

T3

19

T4

13

T5

11

auto[1]

3744

1

T6

2

T7

1

T10

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	33	1			T286	13		T349	20		-	-
values[0]	93	1			T350	3		T260	23		T351	1
values[1]	658	1			T59	23		T110	1		T177	11
values[2]	590	1			T104	10		T187	6		T140	10
values[3]	476	1			T10	4		T62	1		T151	5
values[4]	498	1			T177	25		T239	1		T170	3
values[5]	914	1			T187	3		T143	23		T151	13
values[6]	530	1			T13	6		T72	25		T236	1
values[7]	531	1			T10	5		T18	19		T58	3
values[8]	2928	1			T12	3		T15	2		T16	4
values[9]	1126	1			T7	2		T14	5		T15	12
minimum	13794	1			T3	19		T4	13		T5	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	852	1			T59	23		T110	1		T177	11
values[1]	562	1			T104	10		T151	5		T34	15
values[2]	516	1			T10	4		T62	1		T177	25
values[3]	584	1			T239	1		T170	3		T197	19
values[4]	856	1			T236	1		T187	3		T143	23
values[5]	463	1			T10	3		T58	3		T72	25
values[6]	2739	1			T10	2		T13	6		T15	2
values[7]	723	1			T12	3		T18	19		T59	14
values[8]	862	1			T14	5		T62	1		T140	35
values[9]	196	1			T7	2		T15	12		T191	14
minimum	13818	1			T3	19		T4	13		T5	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

3772

1

T10

1

T13

2

T15

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T110	1		T177	1		T187	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T59	13		T140	3		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T151	1		T51	1		T155	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T104	1		T34	15		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T62	1		T170	10		T154	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T10	4		T177	11		T197	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T144	1		T50	14		T256	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T239	1		T170	3		T197	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T143	12		T42	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T236	1		T187	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	2		T186	1		T73	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T58	3		T72	14		T317	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1525	1			T16	4		T17	1		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T10	1		T13	5		T15	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T62	1		T143	13		T70	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	2		T18	9		T59	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T154	3		T141	8		T242	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T14	5		T62	1		T140	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T7	1		T15	8		T191	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T292	10		T352	12		T353	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13707	1			T3	19		T4	13		T5	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T177	10		T187	5		T262	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T59	10		T140	7		T146	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T151	4		T51	11		T156	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T104	9		T168	15		T298	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T154	10		T246	1		T245	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T177	14		T197	18		T267	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T144	9		T50	14		T266	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T197	9		T39	1		T145	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T143	11		T42	2		T144	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T187	2		T151	12		T154	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T10	1		T73	1		T145	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T72	11		T262	10		T304	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	940	1			T60	8		T61	6		T72	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T10	1		T13	1		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T143	9		T70	3		T158	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	1		T18	10		T59	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T154	11		T141	8		T156	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T140	17		T217	1		T270	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T7	1		T15	4		T256	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T352	9		T353	6		T30	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T6	2		T10	3		T12	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T349	10		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T286	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T350	3		T260	13		T351	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T354	15		T286	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T110	1		T177	1		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T59	13		T146	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T187	1		T51	1		T156	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T104	1		T140	3		T34	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T62	1		T151	1		T170	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T10	4		T197	16		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T144	1		T50	14		T256	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T177	11		T239	1		T170	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T143	12		T144	1		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T187	1		T151	1		T36	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T73	5		T34	4		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	5		T72	14		T236	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	2		T72	9		T186	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	1		T18	9		T58	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1581	1			T16	4		T17	1		T60	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	2		T15	1		T59	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T7	1		T15	8		T191	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T14	5		T62	1		T140	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13690	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T349	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T286	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T260	10		T349	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T354	9		T286	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T177	10		T50	7		T262	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T59	10		T146	11		T248	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T187	5		T51	11		T156	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T104	9		T140	7		T168	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T151	4		T154	10		T246	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T197	18		T298	5		T250	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T144	9		T50	14		T288	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T177	14		T197	9		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T143	11		T144	11		T266	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T187	2		T151	12		T154	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T73	1		T42	2		T244	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	1		T72	11		T262	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T10	1		T72	5		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T10	1		T18	10		T37	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T60	8		T61	6		T111	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	1		T15	1		T59	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T7	1		T15	4		T141	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T140	17		T42	11		T217	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	2		T10	3		T12	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T110	1		T177	11		T187	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T59	11		T140	8		T146	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T151	5		T51	12		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T104	10		T34	1		T168	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T62	1		T170	1		T154	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T10	4		T177	15		T197	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T144	10		T50	15		T256	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T239	1		T170	1		T197	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T143	12		T42	3		T144	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T236	1		T187	3		T151	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T10	2		T186	1		T73	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T58	2		T72	12		T317	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T16	3		T17	1		T60	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T10	2		T13	4		T15	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T62	1		T143	10		T70	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	3		T18	11		T59	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T154	12		T141	9		T242	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T14	5		T62	1		T140	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T7	2		T15	5		T191	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T292	1		T352	10		T353	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13803	1			T3	19		T4	13		T5	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T262	2		T283	14		T161	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T59	12		T140	2		T248	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T155	14		T156	23		T118	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T34	14		T250	11		T268	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T170	9		T154	10		T288	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T177	10		T197	14		T267	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T50	13		T266	1		T148	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T170	2		T197	9		T145	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T143	11		T244	7		T271	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T36	8		T154	9		T259	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T10	1		T73	1		T24	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T58	1		T72	13		T262	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1205	1			T16	1		T72	8		T142	43
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	2		T267	7		T289	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T143	12		T70	3		T191	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T18	8		T59	11		T164	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T154	2		T141	7		T156	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T140	17		T270	6		T25	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T15	7		T191	13		T256	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T292	9		T352	11		T30	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T50	8		T333	7		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T349	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T286	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T350	3		T260	11		T351	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T354	10		T286	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T110	1		T177	11		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T59	11		T146	12		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T187	6		T51	12		T156	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T104	10		T140	8		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T62	1		T151	5		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T10	4		T197	20		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T144	10		T50	15		T256	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T177	15		T239	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T143	12		T144	12		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T187	3		T151	13		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T73	5		T34	1		T42	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T13	4		T72	12		T236	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T10	2		T72	6		T186	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T10	2		T18	11		T58	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T16	3		T17	1		T60	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	3		T15	2		T59	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T7	2		T15	5		T191	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T14	5		T62	1		T140	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13794	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T349	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T286	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T260	12		T349	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T354	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T50	8		T262	2		T283	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T59	12		T248	5		T340	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T156	23		T288	3		T118	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T140	2		T34	14		T268	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T170	9		T154	10		T155	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T197	14		T250	11		T157	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T50	13		T288	4		T342	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T177	10		T170	2		T197	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T143	11		T266	1		T148	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T36	8		T154	9		T145	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T73	1		T34	3		T244	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	2		T72	13		T259	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T10	1		T72	8		T178	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T18	8		T58	1		T267	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T16	1		T142	43		T188	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T59	11		T281	4		T192	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T15	7		T191	22		T141	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T140	17		T164	1		T270	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

auto[0]

3772

1

T10

1

T13

2

T15

7