Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22171

1

T3

19

T4

13

T5

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18619

1

T3

19

T4

13

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3552

1

T10

3

T12

3

T15

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16835

1

T3

19

T4

13

T5

11

auto[1]

5336

1

T10

9

T12

3

T14

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18427

1

T3

19

T4

13

T5

11

auto[1]

3744

1

T6

2

T7

1

T10

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	80	1			T140	10		T342	2		T117	23
values[0]	41	1			T53	4		T298	6		T26	2
values[1]	763	1			T10	2		T104	10		T110	1
values[2]	2677	1			T17	1		T58	3		T59	14
values[3]	691	1			T170	10		T197	22		T34	4
values[4]	517	1			T13	6		T72	14		T186	1
values[5]	511	1			T12	3		T187	3		T42	12
values[6]	600	1			T62	1		T239	1		T187	6
values[7]	666	1			T7	2		T10	3		T68	2
values[8]	654	1			T18	19		T151	5		T36	9
values[9]	1177	1			T10	4		T14	5		T15	14
minimum	13794	1			T3	19		T4	13		T5	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	837	1			T10	2		T58	3		T59	14
values[1]	2748	1			T17	1		T60	9		T61	7
values[2]	697	1			T13	6		T236	1		T170	10
values[3]	585	1			T72	14		T186	1		T187	3
values[4]	455	1			T12	3		T62	1		T239	1
values[5]	645	1			T7	2		T68	2		T178	15
values[6]	663	1			T187	6		T143	22		T37	6
values[7]	605	1			T10	3		T18	19		T62	1
values[8]	999	1			T10	4		T14	5		T15	14
values[9]	128	1			T50	28		T288	7		T193	1
minimum	13809	1			T3	19		T4	13		T5	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

3772

1

T10

1

T13

2

T15

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T10	1		T58	3		T59	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T177	11		T170	3		T140	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1517	1			T17	1		T60	1		T61	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T72	14		T154	3		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T13	5		T236	1		T34	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T170	10		T197	13		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T72	9		T186	1		T187	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T40	1		T154	10		T267	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T239	1		T267	8		T237	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	2		T62	1		T73	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	1		T68	2		T197	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T178	15		T270	7		T312	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T187	1		T37	1		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T143	13		T237	1		T145	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T18	9		T62	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	2		T143	12		T36	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	4		T14	5		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	393	1			T15	8		T59	13		T70	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T193	1		T56	1		T355	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T50	14		T288	5		T279	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13690	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T242	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T10	1		T59	2		T104	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T177	14		T140	17		T144	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	956	1			T60	8		T61	6		T111	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T72	11		T154	11		T51	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	1		T50	11		T255	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T197	9		T39	1		T146	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T72	5		T187	2		T277	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T154	8		T267	6		T254	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T238	6		T246	1		T156	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	1		T73	1		T197	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T197	9		T154	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T270	2		T183	2		T257	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T187	5		T37	5		T144	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T143	9		T145	11		T262	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T18	10		T151	4		T42	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	1		T143	11		T145	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T15	1		T177	10		T266	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T15	4		T59	10		T70	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T56	1		T355	2		T356	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T50	14		T288	2		T322	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	2		T10	3		T12	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T342	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T140	3		T117	13		T279	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T53	3		T298	1		T26	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T314	1		T310	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T10	1		T104	1		T110	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T177	11		T170	3		T140	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1468	1			T17	1		T58	3		T59	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T72	14		T154	3		T164	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T34	4		T50	11		T347	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T170	10		T197	13		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	5		T72	9		T186	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T40	1		T267	8		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T187	1		T267	8		T237	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	2		T42	1		T154	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T239	1		T187	1		T217	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T62	1		T143	13		T178	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	1		T68	2		T197	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T10	2		T312	1		T357	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T18	9		T151	1		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T36	9		T237	1		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T10	4		T14	5		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	444	1			T15	8		T59	13		T143	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13690	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T342	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T140	7		T117	10		T322	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T53	1		T298	5		T358	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T310	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T10	1		T104	9		T25	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T177	14		T140	17		T144	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T59	2		T60	8		T61	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T72	11		T154	11		T241	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T50	11		T255	2		T159	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T197	9		T39	1		T146	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T13	1		T72	5		T261	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T267	6		T321	7		T180	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T187	2		T238	6		T156	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	1		T42	11		T154	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T187	5		T217	1		T246	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T143	9		T73	1		T197	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T7	1		T197	9		T154	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T10	1		T257	8		T287	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T18	10		T151	4		T37	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T145	20		T262	10		T252	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T15	1		T177	10		T266	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T15	4		T59	10		T143	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	2		T10	3		T12	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T10	2		T58	2		T59	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T177	15		T170	1		T140	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T17	1		T60	9		T61	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T72	12		T154	12		T51	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	4		T236	1		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T170	1		T197	10		T39	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T72	6		T186	1		T187	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T40	1		T154	9		T267	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T239	1		T267	1		T237	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	3		T62	1		T73	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	2		T68	2		T197	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T178	1		T270	3		T312	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T187	6		T37	6		T144	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T143	10		T237	1		T145	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T18	11		T62	1		T151	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	2		T143	12		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T10	4		T14	5		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T15	5		T59	11		T70	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T193	1		T56	2		T355	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T50	15		T288	3		T279	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13794	1			T3	19		T4	13		T5	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T242	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T58	1		T59	11		T25	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T177	10		T170	2		T140	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T142	43		T188	16		T290	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T72	13		T154	2		T148	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	2		T34	3		T50	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T170	9		T197	12		T164	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T72	8		T277	3		T288	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T154	9		T267	7		T254	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T267	7		T238	5		T156	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T73	1		T197	2		T342	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T197	9		T154	10		T259	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T178	14		T270	6		T340	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T141	7		T288	3		T340	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T143	12		T145	3		T155	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T18	8		T24	1		T155	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T10	1		T143	11		T36	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T16	1		T266	1		T254	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T15	7		T59	12		T70	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T355	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T50	13		T288	4		T322	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T242	14		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T342	2		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T140	8		T117	11		T279	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T53	3		T298	6		T26	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T314	1		T310	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	2		T104	10		T110	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T177	15		T170	1		T140	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T17	1		T58	2		T59	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T72	12		T154	12		T164	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T34	1		T50	12		T347	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T170	1		T197	10		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	4		T72	6		T186	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T40	1		T267	7		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T187	3		T267	1		T237	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	3		T42	12		T154	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T239	1		T187	6		T217	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T62	1		T143	10		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T7	2		T68	2		T197	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T10	2		T312	1		T357	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T18	11		T151	5		T37	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T36	1		T237	1		T145	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T10	4		T14	5		T15	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T15	5		T59	11		T143	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13794	1			T3	19		T4	13		T5	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T140	2		T117	12		T322	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T53	1		T26	1		T358	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T25	1		T161	10		T332	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T177	10		T170	2		T140	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1148	1			T58	1		T59	11		T142	43
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T72	13		T154	2		T164	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T34	3		T50	10		T249	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T170	9		T197	12		T148	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	2		T72	8		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T267	7		T181	13		T342	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T267	7		T238	5		T156	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T154	9		T270	6		T254	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T277	6		T281	4		T157	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T143	12		T178	14		T73	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T197	9		T154	10		T141	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T10	1		T243	7		T257	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T18	8		T262	2		T332	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T36	8		T145	10		T262	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T16	1		T24	1		T155	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T15	7		T59	12		T143	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18399

1

T3

19

T4

13

T5

11

auto[1]

auto[0]

3772

1

T10

1

T13

2

T15

7