Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5687	1			T4	20		T5	6		T7	20
testmodes[AdcCtrlTestmodeNormal]	4616	1			T5	8		T6	2		T9	8
testmodes[AdcCtrlTestmodeLowpower]	5053	1			T12	1		T60	2		T14	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2909	1			T4	19		T7	19		T8	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1433	1			T5	5		T9	3		T11	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1225	1			T60	1		T32	1		T76	17
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1445	1			T5	5		T9	2		T11	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1615	1			T5	3		T6	1		T9	5
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1225	1			T12	1		T15	1		T19	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1218	1			T60	2		T19	1		T76	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1234	1			T12	1		T14	1		T62	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2354	1			T14	2		T15	1		T27	14