Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.07	96.67	100.00	100.00	98.83	98.33	91.24

Total tests in report: 920

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
67.42	67.42	95.28	95.28	77.36	77.36	94.08	94.08	21.62	21.62	92.65	92.65	83.81	83.81	7.19	7.19	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2266214281
75.56	8.14	97.90	2.62	86.95	9.59	94.55	0.47	51.35	29.73	96.54	3.89	88.65	4.84	13.00	5.81	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.2570051787
80.39	4.83	98.61	0.71	89.30	2.35	96.80	2.25	70.27	18.92	97.96	1.42	89.15	0.50	20.66	7.66	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1071178268
83.25	2.85	98.61	0.00	89.34	0.04	96.80	0.00	89.19	18.92	98.02	0.06	89.15	0.00	21.61	0.95	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.3586880544
85.08	1.83	98.61	0.00	93.54	4.20	97.04	0.24	89.19	0.00	98.08	0.06	89.48	0.33	29.60	7.99	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.3499118530
86.32	1.24	98.86	0.25	93.82	0.29	97.04	0.00	94.59	5.41	98.45	0.37	89.65	0.17	31.82	2.22	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2103258678
87.50	1.18	98.86	0.00	93.82	0.00	97.04	0.00	94.59	0.00	98.45	0.00	89.65	0.00	40.08	8.26	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.2540266125
88.38	0.88	98.86	0.00	93.82	0.00	97.04	0.00	94.59	0.00	98.45	0.00	89.65	0.00	46.22	6.14	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.2137136911
89.15	0.77	98.86	0.00	93.82	0.00	97.04	0.00	94.59	0.00	98.45	0.00	89.65	0.00	51.61	5.39	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.1602827020
89.89	0.74	98.86	0.00	93.82	0.00	97.04	0.00	94.59	0.00	98.45	0.00	93.66	4.01	52.81	1.20	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.421432490
90.51	0.62	98.86	0.00	93.82	0.00	97.04	0.00	94.59	0.00	98.45	0.00	93.82	0.17	56.98	4.17	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.2923041608
91.04	0.53	98.86	0.00	93.82	0.00	97.04	0.00	94.59	0.00	98.45	0.00	94.32	0.50	60.19	3.22	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.14841027
91.57	0.53	98.89	0.03	93.91	0.08	97.16	0.12	97.30	2.70	98.52	0.06	94.99	0.67	60.22	0.02	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.362734434
92.05	0.49	98.89	0.00	93.91	0.00	97.16	0.00	100.00	2.70	98.52	0.00	94.99	0.00	60.92	0.70	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2599435582
92.52	0.47	98.89	0.00	95.35	1.44	97.63	0.47	100.00	0.00	98.58	0.06	95.66	0.67	61.57	0.65	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3048921228
92.99	0.47	98.89	0.00	95.88	0.54	97.63	0.00	100.00	0.00	98.58	0.00	95.66	0.00	64.29	2.72	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.1262186767
93.40	0.41	98.92	0.03	96.01	0.12	99.76	2.13	100.00	0.00	98.70	0.12	95.99	0.33	64.41	0.12	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.1945874411
93.80	0.40	98.92	0.00	96.01	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.16	0.17	67.06	2.65	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.863383353
94.13	0.32	98.92	0.00	96.01	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.16	0.00	69.33	2.27	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1822314657
94.42	0.29	98.92	0.00	96.01	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.33	0.17	71.23	1.90	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.61706201
94.70	0.27	98.92	0.00	96.01	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.33	0.00	73.15	1.92	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.3795412043
94.93	0.24	98.92	0.00	96.01	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.33	0.00	74.82	1.67	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.2192349122
95.14	0.21	98.92	0.00	96.01	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.33	0.00	76.29	1.47	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.3305085599
95.35	0.20	98.98	0.06	96.25	0.25	99.76	0.00	100.00	0.00	98.83	0.12	97.33	1.00	76.29	0.00	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.123368884
95.53	0.18	98.98	0.00	96.25	0.00	99.76	0.00	100.00	0.00	98.83	0.00	97.66	0.33	77.19	0.90	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3445806479
95.68	0.16	98.98	0.00	96.25	0.00	99.76	0.00	100.00	0.00	98.83	0.00	97.66	0.00	78.29	1.10	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.3763911947
95.82	0.14	98.98	0.00	96.25	0.00	99.76	0.00	100.00	0.00	98.83	0.00	97.66	0.00	79.24	0.95	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.3438884086
95.95	0.13	98.98	0.00	96.25	0.00	99.76	0.00	100.00	0.00	98.83	0.00	98.00	0.33	79.84	0.60	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.2706331948
96.07	0.12	98.98	0.00	96.25	0.00	99.76	0.00	100.00	0.00	98.83	0.00	98.00	0.00	80.66	0.82	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_both.3428694353
96.16	0.10	98.98	0.00	96.25	0.00	99.76	0.00	100.00	0.00	98.83	0.00	98.00	0.00	81.33	0.67	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.3952189135
96.26	0.10	98.98	0.00	96.25	0.00	99.76	0.00	100.00	0.00	98.83	0.00	98.00	0.00	82.01	0.67	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.3787721179
96.34	0.07	98.98	0.00	96.25	0.00	99.76	0.00	100.00	0.00	98.83	0.00	98.00	0.00	82.53	0.52	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.2647759347
96.41	0.07	98.98	0.00	96.25	0.00	99.76	0.00	100.00	0.00	98.83	0.00	98.00	0.00	83.05	0.52	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.3379648471
96.49	0.07	98.98	0.00	96.25	0.00	99.76	0.00	100.00	0.00	98.83	0.00	98.00	0.00	83.58	0.52	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_clock_gating.4138577657
96.55	0.06	99.07	0.09	96.38	0.12	100.00	0.24	100.00	0.00	98.83	0.00	98.00	0.00	83.58	0.00	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.3500438576
96.61	0.06	99.07	0.00	96.38	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.00	0.00	84.03	0.45	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.1413480868
96.68	0.06	99.07	0.00	96.38	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.00	0.00	84.45	0.42	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.63148028
96.74	0.06	99.07	0.00	96.62	0.25	100.00	0.00	100.00	0.00	98.83	0.00	98.00	0.00	84.63	0.17	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3670847757
96.79	0.05	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.00	0.00	84.98	0.35	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.3200161895
96.84	0.05	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.00	0.00	85.33	0.35	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt.1828456978
96.88	0.05	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.33	85.33	0.00	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.669806207
96.93	0.05	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	85.65	0.32	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.4163414778
96.98	0.05	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	85.97	0.32	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.2408750137
97.02	0.05	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	86.30	0.32	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_clock_gating.4051973536
97.06	0.04	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	86.60	0.30	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.2319719566
97.10	0.04	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	86.87	0.27	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all.2294095872
97.14	0.04	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	87.12	0.25	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_both.618496448
97.18	0.04	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	87.37	0.25	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.2438411662
97.21	0.03	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	87.60	0.22	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.3720602622
97.24	0.03	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	87.82	0.22	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_clock_gating.860903272
97.27	0.03	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.02	0.20	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.1690473195
97.30	0.03	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.22	0.20	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.1918396089
97.32	0.02	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.40	0.17	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.2028825942
97.35	0.02	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.57	0.17	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.3192366265
97.37	0.02	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.74	0.17	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup.4267775116
97.39	0.02	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.89	0.15	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.1790839527
97.41	0.02	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.04	0.15	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_both.519372981
97.44	0.02	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.19	0.15	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_both.3940266994
97.46	0.02	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.34	0.15	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.997181223
97.47	0.02	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.47	0.12	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all.1357963690
97.49	0.02	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.59	0.12	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.849474370
97.51	0.02	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.72	0.12	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.112433791
97.52	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.82	0.10	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1319633899
97.54	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.92	0.10	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.4214489636
97.55	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.02	0.10	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.2078620640
97.57	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.12	0.10	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_both.2680328388
97.58	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.22	0.10	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_clock_gating.2832575224
97.59	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.29	0.07	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.1952127049
97.60	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.37	0.07	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup.179858749
97.61	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.44	0.07	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_both.2621790927
97.62	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.52	0.07	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3266847455
97.64	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.59	0.07	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_fsm_reset.1441590876
97.65	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.67	0.07	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.2886346139
97.66	0.01	99.07	0.00	96.67	0.04	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.69	0.02	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.975571889
97.66	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.74	0.05	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.1651481554
97.67	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.79	0.05	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.2232315299
97.68	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.84	0.05	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled.3242448922
97.68	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.89	0.05	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_fsm_reset.692375733
97.69	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.94	0.05	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_clock_gating.1012486879
97.70	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.99	0.05	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled.2600261502
97.70	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.02	0.02	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2777388993
97.71	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.04	0.02	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.1267041402
97.71	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.07	0.02	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.1540374882
97.71	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.09	0.02	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.2464277264
97.72	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.12	0.02	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_fsm_reset.1535444798
97.72	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.14	0.02	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup.940280467
97.72	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.17	0.02	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_both.1129954836
97.73	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.19	0.02	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_clock_gating.4181249300
97.73	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.22	0.02	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_both.917961579
97.73	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.24	0.02	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_clock_gating.652484525

---

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3776290357
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2028292531
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.124662633
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1934634351
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.3990166954
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2722066181
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.308743871
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2182857008
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.451056399
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1967916035
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.2396526676
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4070583374
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.451803278
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2555227523
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2188521602
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3390500091
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.2175535618
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3009499179
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1147498146
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.875120357
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3115039170
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3063158369
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.2557653401
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3227561522
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3887998825
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3499479025
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2324379818
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3200254833
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.2622902348
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2220817931
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.488402925
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.22923101
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3393178598
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.93446872
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.958104780
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2546267072
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1785326178
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.787249616
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.561856246
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1796548179
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.1587557975
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1005310192
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2013424047
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.321632614
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2701869689
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.3892207253
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3087866610
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2199205388
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1334862077
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.509507584
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2133465570
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.740173296
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1318814415
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3786900350
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1345569540
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4139183967
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.812792955
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.3808991487
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1308269393
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1804104740
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3452637222
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2607052117
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4099093379
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.821747118
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2570968291
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1933725709
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1496530
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2121266500
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1429603617
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.2406428036
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2310119357
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4273408494
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2504792780
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1689866653
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4858481
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3721109599
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1011870691
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.156223318
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.1420370344
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3065195646
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1348096672
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2537376701
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.2429745781
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.4250243699
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.2211982227
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/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.3345074547
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.2754758695
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.3269931999
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1774645512
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.285858692
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.928762002
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.1689510806
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.873456658
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.2099670202
/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.414102688

---

Total test records in report: 920

---

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

---

TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.1516684543			Aug 27 05:36:42 AM UTC 24	Aug 27 05:36:44 AM UTC 24	417110582 ps
T2	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.3500438576			Aug 27 05:36:45 AM UTC 24	Aug 27 05:36:50 AM UTC 24	407988408 ps
T3	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.1905085230			Aug 27 05:36:48 AM UTC 24	Aug 27 05:36:51 AM UTC 24	456363153 ps
T4	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.2012254329			Aug 27 05:36:45 AM UTC 24	Aug 27 05:36:53 AM UTC 24	5887297225 ps
T5	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.4087959500			Aug 27 05:36:42 AM UTC 24	Aug 27 05:36:53 AM UTC 24	3461652527 ps
T6	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2266214281			Aug 27 05:36:42 AM UTC 24	Aug 27 05:36:53 AM UTC 24	6916351484 ps
T7	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.2009798261			Aug 27 05:36:38 AM UTC 24	Aug 27 05:36:55 AM UTC 24	5929953625 ps
T24	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.1945874411			Aug 27 05:36:47 AM UTC 24	Aug 27 05:36:57 AM UTC 24	8114414039 ps
T8	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.4098127580			Aug 27 05:36:49 AM UTC 24	Aug 27 05:36:57 AM UTC 24	6169414344 ps
T9	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.362734434			Aug 27 05:36:45 AM UTC 24	Aug 27 05:36:58 AM UTC 24	3610751086 ps
T10	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.2877708843			Aug 27 05:36:42 AM UTC 24	Aug 27 05:37:00 AM UTC 24	6001128114 ps
T11	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.4057720399			Aug 27 05:36:45 AM UTC 24	Aug 27 05:37:02 AM UTC 24	2995859395 ps
T25	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.2833781890			Aug 27 05:36:58 AM UTC 24	Aug 27 05:37:02 AM UTC 24	422063877 ps
T26	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.3812862807			Aug 27 05:36:58 AM UTC 24	Aug 27 05:37:05 AM UTC 24	4515823316 ps
T12	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1071178268			Aug 27 05:36:55 AM UTC 24	Aug 27 05:37:06 AM UTC 24	3764925895 ps
T65	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.3602668573			Aug 27 05:36:42 AM UTC 24	Aug 27 05:37:08 AM UTC 24	8078478091 ps
T13	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.1059889646			Aug 27 05:36:53 AM UTC 24	Aug 27 05:37:09 AM UTC 24	5676576314 ps
T69	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.131015562			Aug 27 05:36:58 AM UTC 24	Aug 27 05:37:09 AM UTC 24	6031032139 ps
T70	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.2947866826			Aug 27 05:37:08 AM UTC 24	Aug 27 05:37:11 AM UTC 24	4681986252 ps
T66	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.3279353423			Aug 27 05:36:45 AM UTC 24	Aug 27 05:37:12 AM UTC 24	8009551718 ps
T71	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.1322138577			Aug 27 05:37:13 AM UTC 24	Aug 27 05:37:16 AM UTC 24	409700244 ps
T72	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.2522276882			Aug 27 05:37:11 AM UTC 24	Aug 27 05:37:17 AM UTC 24	8043420052 ps
T60	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1077170016			Aug 27 05:37:09 AM UTC 24	Aug 27 05:37:27 AM UTC 24	10013376068 ps
T61	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.3130347011			Aug 27 05:37:13 AM UTC 24	Aug 27 05:37:30 AM UTC 24	5635946260 ps
T14	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2578148299			Aug 27 05:36:45 AM UTC 24	Aug 27 05:37:31 AM UTC 24	5931747661 ps
T15	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1908482676			Aug 27 05:36:47 AM UTC 24	Aug 27 05:37:36 AM UTC 24	8000448378 ps
T16	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.1308918801			Aug 27 05:37:00 AM UTC 24	Aug 27 05:37:43 AM UTC 24	163713185335 ps
T27	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.3724215882			Aug 27 05:36:53 AM UTC 24	Aug 27 05:37:52 AM UTC 24	34298057968 ps
T17	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.1700078062			Aug 27 05:36:45 AM UTC 24	Aug 27 05:37:52 AM UTC 24	323259821397 ps
T28	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.890916105			Aug 27 05:36:45 AM UTC 24	Aug 27 05:37:56 AM UTC 24	22332411293 ps
T29	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.3479213425			Aug 27 05:36:42 AM UTC 24	Aug 27 05:38:05 AM UTC 24	28627148615 ps
T18	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.3369863753			Aug 27 05:37:02 AM UTC 24	Aug 27 05:38:07 AM UTC 24	166053568386 ps
T30	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.2752108455			Aug 27 05:37:53 AM UTC 24	Aug 27 05:38:08 AM UTC 24	3065560083 ps
T31	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.870265375			Aug 27 05:38:08 AM UTC 24	Aug 27 05:38:11 AM UTC 24	313906665 ps
T19	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2103258678			Aug 27 05:38:05 AM UTC 24	Aug 27 05:38:19 AM UTC 24	41500184890 ps
T97	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.1491823874			Aug 27 05:36:42 AM UTC 24	Aug 27 05:38:20 AM UTC 24	87401772754 ps
T112	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.1474443595			Aug 27 05:38:12 AM UTC 24	Aug 27 05:38:21 AM UTC 24	6110008423 ps
T20	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.3499118530			Aug 27 05:36:52 AM UTC 24	Aug 27 05:38:24 AM UTC 24	487955674245 ps
T147	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.1777368119			Aug 27 05:36:45 AM UTC 24	Aug 27 05:38:37 AM UTC 24	43194229298 ps
T21	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.2570051787			Aug 27 05:36:45 AM UTC 24	Aug 27 05:38:40 AM UTC 24	172578660599 ps
T22	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.3952189135			Aug 27 05:36:53 AM UTC 24	Aug 27 05:39:02 AM UTC 24	189061960793 ps
T23	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3230756453			Aug 27 05:36:45 AM UTC 24	Aug 27 05:39:05 AM UTC 24	217739274089 ps
T67	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.2137136911			Aug 27 05:36:56 AM UTC 24	Aug 27 05:39:11 AM UTC 24	497548394841 ps
T68	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.4214489636			Aug 27 05:36:45 AM UTC 24	Aug 27 05:39:21 AM UTC 24	342801869883 ps
T96	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2002914767			Aug 27 05:36:52 AM UTC 24	Aug 27 05:39:28 AM UTC 24	202003929816 ps
T179	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.2938207863			Aug 27 05:37:09 AM UTC 24	Aug 27 05:39:28 AM UTC 24	36387427288 ps
T180	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.2303601372			Aug 27 05:39:05 AM UTC 24	Aug 27 05:39:28 AM UTC 24	4841183758 ps
T181	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.3121451049			Aug 27 05:37:53 AM UTC 24	Aug 27 05:39:29 AM UTC 24	42861419149 ps
T182	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.1727821891			Aug 27 05:39:29 AM UTC 24	Aug 27 05:39:31 AM UTC 24	503511567 ps
T62	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3491871439			Aug 27 05:39:21 AM UTC 24	Aug 27 05:39:39 AM UTC 24	4062943314 ps
T159	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1457756773			Aug 27 05:36:45 AM UTC 24	Aug 27 05:39:42 AM UTC 24	163029468309 ps
T183	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.729597691			Aug 27 05:39:29 AM UTC 24	Aug 27 05:39:43 AM UTC 24	5913662366 ps
T184	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.4228407234			Aug 27 05:39:05 AM UTC 24	Aug 27 05:39:47 AM UTC 24	24568773559 ps
T160	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.440785500			Aug 27 05:36:49 AM UTC 24	Aug 27 05:40:01 AM UTC 24	330280155778 ps
T84	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.61706201			Aug 27 05:36:45 AM UTC 24	Aug 27 05:40:09 AM UTC 24	385386403196 ps
T136	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.267212579			Aug 27 05:39:02 AM UTC 24	Aug 27 05:40:12 AM UTC 24	175397119921 ps
T143	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.3539393079			Aug 27 05:39:32 AM UTC 24	Aug 27 05:40:19 AM UTC 24	163083186687 ps
T144	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3445806479			Aug 27 05:37:28 AM UTC 24	Aug 27 05:40:21 AM UTC 24	320684242284 ps
T168	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.125562195			Aug 27 05:36:47 AM UTC 24	Aug 27 05:40:22 AM UTC 24	168517644791 ps
T169	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.124090502			Aug 27 05:40:13 AM UTC 24	Aug 27 05:40:30 AM UTC 24	3738757697 ps
T63	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2668518223			Aug 27 05:40:23 AM UTC 24	Aug 27 05:40:32 AM UTC 24	1247322879 ps
T170	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.2367594185			Aug 27 05:40:33 AM UTC 24	Aug 27 05:40:36 AM UTC 24	511805894 ps
T156	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.1452959923			Aug 27 05:37:20 AM UTC 24	Aug 27 05:40:39 AM UTC 24	319901656872 ps
T393	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.2335450412			Aug 27 05:40:37 AM UTC 24	Aug 27 05:41:02 AM UTC 24	5800116823 ps
T237	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.567323873			Aug 27 05:36:53 AM UTC 24	Aug 27 05:41:05 AM UTC 24	182458692002 ps
T200	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.670981085			Aug 27 05:36:50 AM UTC 24	Aug 27 05:41:22 AM UTC 24	320596269367 ps
T145	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.2388843714			Aug 27 05:36:39 AM UTC 24	Aug 27 05:41:27 AM UTC 24	318213558264 ps
T52	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.863383353			Aug 27 05:38:07 AM UTC 24	Aug 27 05:41:42 AM UTC 24	337486019750 ps
T54	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.2438411662			Aug 27 05:37:01 AM UTC 24	Aug 27 05:41:52 AM UTC 24	169613410954 ps
T55	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.788857458			Aug 27 05:39:42 AM UTC 24	Aug 27 05:41:56 AM UTC 24	330254506716 ps
T56	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3703863232			Aug 27 05:36:39 AM UTC 24	Aug 27 05:41:58 AM UTC 24	155009002889 ps
T57	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.451218866			Aug 27 05:40:20 AM UTC 24	Aug 27 05:42:06 AM UTC 24	32257353358 ps
T58	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.101710775			Aug 27 05:41:59 AM UTC 24	Aug 27 05:42:07 AM UTC 24	3797829264 ps
T59	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.2247367339			Aug 27 05:41:03 AM UTC 24	Aug 27 05:42:25 AM UTC 24	328992568289 ps
T32	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1418241706			Aug 27 05:42:26 AM UTC 24	Aug 27 05:42:50 AM UTC 24	5229423240 ps
T42	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.1262186767			Aug 27 05:36:42 AM UTC 24	Aug 27 05:42:53 AM UTC 24	353513624186 ps
T43	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.1299723491			Aug 27 05:42:54 AM UTC 24	Aug 27 05:42:58 AM UTC 24	504751903 ps
T44	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.873456658			Aug 27 05:42:59 AM UTC 24	Aug 27 05:43:28 AM UTC 24	6152126456 ps
T45	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2347349035			Aug 27 05:37:00 AM UTC 24	Aug 27 05:43:30 AM UTC 24	330191478727 ps
T46	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.323704603			Aug 27 05:36:52 AM UTC 24	Aug 27 05:43:32 AM UTC 24	195326180946 ps
T47	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.1486944221			Aug 27 05:40:40 AM UTC 24	Aug 27 05:43:41 AM UTC 24	162891010932 ps
T48	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.2021913653			Aug 27 05:42:07 AM UTC 24	Aug 27 05:43:51 AM UTC 24	28641184725 ps
T49	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.4112633774			Aug 27 05:37:02 AM UTC 24	Aug 27 05:43:56 AM UTC 24	610774551250 ps
T50	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.4163414778			Aug 27 05:36:40 AM UTC 24	Aug 27 05:44:11 AM UTC 24	604782259878 ps
T394	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.1016022628			Aug 27 05:38:21 AM UTC 24	Aug 27 05:44:15 AM UTC 24	339560926633 ps
T76	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.1144480726			Aug 27 05:36:45 AM UTC 24	Aug 27 05:44:23 AM UTC 24	104098223594 ps
T137	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.540829395			Aug 27 05:38:33 AM UTC 24	Aug 27 05:44:44 AM UTC 24	371853440286 ps
T395	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.1689510806			Aug 27 05:44:24 AM UTC 24	Aug 27 05:44:44 AM UTC 24	4753514439 ps
T73	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.2057197665			Aug 27 05:36:55 AM UTC 24	Aug 27 05:44:46 AM UTC 24	121565371113 ps
T77	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.1651481554			Aug 27 05:36:42 AM UTC 24	Aug 27 05:44:48 AM UTC 24	114982177106 ps
T249	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.3680050664			Aug 27 05:37:18 AM UTC 24	Aug 27 05:44:57 AM UTC 24	164819675002 ps
T396	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.733681576			Aug 27 05:44:57 AM UTC 24	Aug 27 05:45:01 AM UTC 24	487571208 ps
T238	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.2861474826			Aug 27 05:37:37 AM UTC 24	Aug 27 05:45:12 AM UTC 24	166958000164 ps
T64	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.414102688			Aug 27 05:44:47 AM UTC 24	Aug 27 05:45:20 AM UTC 24	11752268892 ps
T397	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.2275274334			Aug 27 05:36:38 AM UTC 24	Aug 27 05:45:21 AM UTC 24	323731950580 ps
T398	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.4186644019			Aug 27 05:37:18 AM UTC 24	Aug 27 05:45:24 AM UTC 24	164143056896 ps
T399	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.1243679676			Aug 27 05:45:01 AM UTC 24	Aug 27 05:45:24 AM UTC 24	6002583518 ps
T400	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.928762002			Aug 27 05:44:45 AM UTC 24	Aug 27 05:45:25 AM UTC 24	39186431317 ps
T239	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.333139948			Aug 27 05:37:11 AM UTC 24	Aug 27 05:45:29 AM UTC 24	204664478347 ps
T401	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1069145346			Aug 27 05:39:47 AM UTC 24	Aug 27 05:45:56 AM UTC 24	406195610438 ps
T219	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.2983525631			Aug 27 05:37:56 AM UTC 24	Aug 27 05:45:56 AM UTC 24	79347840578 ps
T402	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.2838163669			Aug 27 05:45:57 AM UTC 24	Aug 27 05:46:02 AM UTC 24	2879795770 ps
T161	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.3988154516			Aug 27 05:36:45 AM UTC 24	Aug 27 05:46:04 AM UTC 24	164296580042 ps
T247	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.32382049			Aug 27 05:36:40 AM UTC 24	Aug 27 05:46:15 AM UTC 24	178166320593 ps
T74	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.3586880544			Aug 27 05:37:09 AM UTC 24	Aug 27 05:46:18 AM UTC 24	102333561963 ps
T403	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2739487075			Aug 27 05:38:25 AM UTC 24	Aug 27 05:46:20 AM UTC 24	165207099292 ps
T157	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.386038690			Aug 27 05:37:02 AM UTC 24	Aug 27 05:46:21 AM UTC 24	209413916136 ps
T404	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.2042427895			Aug 27 05:46:21 AM UTC 24	Aug 27 05:46:25 AM UTC 24	505356451 ps
T405	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.726084963			Aug 27 05:46:21 AM UTC 24	Aug 27 05:46:28 AM UTC 24	5862401592 ps
T146	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1723816871			Aug 27 05:46:15 AM UTC 24	Aug 27 05:46:29 AM UTC 24	4897544382 ps
T406	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.4137886256			Aug 27 05:46:02 AM UTC 24	Aug 27 05:46:56 AM UTC 24	33265733848 ps
T246	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.256537911			Aug 27 05:36:38 AM UTC 24	Aug 27 05:47:04 AM UTC 24	167632157397 ps
T138	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.3345074547			Aug 27 05:43:28 AM UTC 24	Aug 27 05:47:10 AM UTC 24	485779708934 ps
T148	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.3983041723			Aug 27 05:38:20 AM UTC 24	Aug 27 05:47:13 AM UTC 24	483316453931 ps
T75	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2086761319			Aug 27 05:39:11 AM UTC 24	Aug 27 05:47:48 AM UTC 24	89255844212 ps
T139	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.498655698			Aug 27 05:38:42 AM UTC 24	Aug 27 05:48:07 AM UTC 24	409821380234 ps
T194	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.3841446562			Aug 27 05:48:08 AM UTC 24	Aug 27 05:48:14 AM UTC 24	2855434790 ps
T195	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.3232299337			Aug 27 05:36:45 AM UTC 24	Aug 27 05:48:17 AM UTC 24	138520646062 ps
T196	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1822314657			Aug 27 05:47:14 AM UTC 24	Aug 27 05:48:38 AM UTC 24	496485146082 ps
T197	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.977495285			Aug 27 05:48:38 AM UTC 24	Aug 27 05:48:46 AM UTC 24	4871202523 ps
T198	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.1214451090			Aug 27 05:48:14 AM UTC 24	Aug 27 05:48:48 AM UTC 24	28319876066 ps
T199	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.628752259			Aug 27 05:48:49 AM UTC 24	Aug 27 05:48:52 AM UTC 24	396375775 ps
T243	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.842585803			Aug 27 05:41:06 AM UTC 24	Aug 27 05:48:56 AM UTC 24	167639760903 ps
T407	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.2373356144			Aug 27 05:48:53 AM UTC 24	Aug 27 05:49:05 AM UTC 24	5942099539 ps
T140	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.3763911947			Aug 27 05:36:45 AM UTC 24	Aug 27 05:49:08 AM UTC 24	553951436029 ps
T149	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.4135259924			Aug 27 05:41:56 AM UTC 24	Aug 27 05:49:19 AM UTC 24	335604269627 ps
T408	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.2754758695			Aug 27 05:43:31 AM UTC 24	Aug 27 05:49:27 AM UTC 24	162777597267 ps
T150	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.3305085599			Aug 27 05:39:40 AM UTC 24	Aug 27 05:49:34 AM UTC 24	485459532619 ps
T409	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1774645512			Aug 27 05:43:57 AM UTC 24	Aug 27 05:49:36 AM UTC 24	605546474420 ps
T223	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.433068757			Aug 27 05:42:09 AM UTC 24	Aug 27 05:49:55 AM UTC 24	97431608945 ps
T250	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.2512232179			Aug 27 05:40:10 AM UTC 24	Aug 27 05:50:01 AM UTC 24	184025717302 ps
T261	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.1732312316			Aug 27 05:44:16 AM UTC 24	Aug 27 05:50:02 AM UTC 24	170593170146 ps
T410	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3757758508			Aug 27 05:45:26 AM UTC 24	Aug 27 05:50:09 AM UTC 24	403567864492 ps
T411	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.1819503804			Aug 27 05:50:01 AM UTC 24	Aug 27 05:50:12 AM UTC 24	4775770587 ps
T185	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.3976791846			Aug 27 05:45:57 AM UTC 24	Aug 27 05:50:15 AM UTC 24	375332657477 ps
T171	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1080356302			Aug 27 05:50:14 AM UTC 24	Aug 27 05:50:19 AM UTC 24	8740851809 ps
T211	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.911447761			Aug 27 05:50:21 AM UTC 24	Aug 27 05:50:24 AM UTC 24	307207634 ps
T212	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.2408750137			Aug 27 05:36:45 AM UTC 24	Aug 27 05:50:24 AM UTC 24	402720264665 ps
T213	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.830331353			Aug 27 05:50:25 AM UTC 24	Aug 27 05:50:28 AM UTC 24	6084888929 ps
T141	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.3309218838			Aug 27 05:41:27 AM UTC 24	Aug 27 05:50:32 AM UTC 24	621197854090 ps
T214	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.3154245777			Aug 27 05:40:21 AM UTC 24	Aug 27 05:50:42 AM UTC 24	109409987433 ps
T215	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.70718771			Aug 27 05:36:52 AM UTC 24	Aug 27 05:50:56 AM UTC 24	497681874672 ps
T216	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.740128352			Aug 27 05:36:45 AM UTC 24	Aug 27 05:51:03 AM UTC 24	331132237555 ps
T217	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.3052334649			Aug 27 05:36:58 AM UTC 24	Aug 27 05:51:09 AM UTC 24	331835892922 ps
T412	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.2648297455			Aug 27 05:45:20 AM UTC 24	Aug 27 05:51:22 AM UTC 24	324043857695 ps
T244	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.3119515247			Aug 27 05:40:02 AM UTC 24	Aug 27 05:51:34 AM UTC 24	333721356791 ps
T413	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.3892373175			Aug 27 05:46:30 AM UTC 24	Aug 27 05:51:34 AM UTC 24	325369321316 ps
T414	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.1133942420			Aug 27 05:50:02 AM UTC 24	Aug 27 05:51:36 AM UTC 24	36290811956 ps
T415	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.929063578			Aug 27 05:51:34 AM UTC 24	Aug 27 05:51:45 AM UTC 24	3407003944 ps
T142	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.3402928803			Aug 27 05:37:32 AM UTC 24	Aug 27 05:51:55 AM UTC 24	400323105764 ps
T262	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.3750024056			Aug 27 05:49:09 AM UTC 24	Aug 27 05:52:00 AM UTC 24	167934412715 ps
T416	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.1848896322			Aug 27 05:52:00 AM UTC 24	Aug 27 05:52:02 AM UTC 24	507960314 ps
T417	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.974944839			Aug 27 05:45:25 AM UTC 24	Aug 27 05:52:04 AM UTC 24	165235816751 ps
T418	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.1789322138			Aug 27 05:52:03 AM UTC 24	Aug 27 05:52:10 AM UTC 24	5912956034 ps
T419	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.2868202684			Aug 27 05:51:36 AM UTC 24	Aug 27 05:52:23 AM UTC 24	35400609461 ps
T270	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1652322587			Aug 27 05:51:47 AM UTC 24	Aug 27 05:52:27 AM UTC 24	25778712878 ps
T266	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.908318661			Aug 27 05:43:33 AM UTC 24	Aug 27 05:52:37 AM UTC 24	162426599093 ps
T234	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.905304353			Aug 27 05:46:05 AM UTC 24	Aug 27 05:52:58 AM UTC 24	74669169025 ps
T260	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.371727672			Aug 27 05:36:42 AM UTC 24	Aug 27 05:52:58 AM UTC 24	440915041952 ps
T158	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.1100186057			Aug 27 05:51:22 AM UTC 24	Aug 27 05:53:03 AM UTC 24	197288221003 ps
T162	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.3878320906			Aug 27 05:36:45 AM UTC 24	Aug 27 05:53:05 AM UTC 24	348586152450 ps
T420	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.585249884			Aug 27 05:51:04 AM UTC 24	Aug 27 05:53:20 AM UTC 24	192544297025 ps
T257	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.3787721179			Aug 27 05:37:44 AM UTC 24	Aug 27 05:53:22 AM UTC 24	336272079220 ps
T421	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.2657351838			Aug 27 05:53:06 AM UTC 24	Aug 27 05:53:24 AM UTC 24	4265734183 ps
T241	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.2550962013			Aug 27 05:46:30 AM UTC 24	Aug 27 05:53:26 AM UTC 24	160541125616 ps
T279	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1319633899			Aug 27 05:53:25 AM UTC 24	Aug 27 05:53:35 AM UTC 24	23003983264 ps
T422	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.480617912			Aug 27 05:53:36 AM UTC 24	Aug 27 05:53:39 AM UTC 24	326049620 ps
T236	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.1690473195			Aug 27 05:50:25 AM UTC 24	Aug 27 05:53:48 AM UTC 24	329871830013 ps
T423	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1927834038			Aug 27 05:50:43 AM UTC 24	Aug 27 05:53:57 AM UTC 24	337310485008 ps
T424	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1997396509			Aug 27 05:41:23 AM UTC 24	Aug 27 05:53:59 AM UTC 24	325082903352 ps
T425	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2702764749			Aug 27 05:49:20 AM UTC 24	Aug 27 05:54:01 AM UTC 24	490364603936 ps
T426	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.550029144			Aug 27 05:53:40 AM UTC 24	Aug 27 05:54:07 AM UTC 24	5984806442 ps
T201	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.2540266125			Aug 27 05:41:52 AM UTC 24	Aug 27 05:54:09 AM UTC 24	496467212296 ps
T248	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.1602827020			Aug 27 05:36:45 AM UTC 24	Aug 27 05:54:10 AM UTC 24	496038792238 ps
T245	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.2647759347			Aug 27 05:45:26 AM UTC 24	Aug 27 05:54:19 AM UTC 24	542768243305 ps
T320	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.1295916479			Aug 27 05:52:37 AM UTC 24	Aug 27 05:54:34 AM UTC 24	188293943665 ps
T228	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.285858692			Aug 27 05:44:45 AM UTC 24	Aug 27 05:54:34 AM UTC 24	96876749663 ps
T202	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.3261623120			Aug 27 05:50:33 AM UTC 24	Aug 27 05:54:38 AM UTC 24	325684405977 ps
T427	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.2729432047			Aug 27 05:54:35 AM UTC 24	Aug 27 05:54:42 AM UTC 24	4994791150 ps
T311	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1167901137			Aug 27 05:54:43 AM UTC 24	Aug 27 05:54:50 AM UTC 24	18895506975 ps
T240	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.2218828111			Aug 27 05:45:13 AM UTC 24	Aug 27 05:54:55 AM UTC 24	490478538836 ps
T428	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.546213182			Aug 27 05:52:11 AM UTC 24	Aug 27 05:54:56 AM UTC 24	498838542975 ps
T429	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.4107510818			Aug 27 05:54:56 AM UTC 24	Aug 27 05:54:58 AM UTC 24	319918031 ps
T163	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.1413480868			Aug 27 05:51:56 AM UTC 24	Aug 27 05:55:04 AM UTC 24	384192013431 ps
T430	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.2509415123			Aug 27 05:54:57 AM UTC 24	Aug 27 05:55:05 AM UTC 24	5842204393 ps
T265	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.3269931999			Aug 27 05:43:52 AM UTC 24	Aug 27 05:55:28 AM UTC 24	403753635416 ps
T431	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3399941194			Aug 27 05:52:58 AM UTC 24	Aug 27 05:55:51 AM UTC 24	197988221216 ps
T432	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1346814144			Aug 27 05:38:37 AM UTC 24	Aug 27 05:55:57 AM UTC 24	412295780704 ps
T433	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.2416807621			Aug 27 05:54:36 AM UTC 24	Aug 27 05:56:04 AM UTC 24	35612555799 ps
T434	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.1520306220			Aug 27 05:53:21 AM UTC 24	Aug 27 05:56:04 AM UTC 24	41636213011 ps
T280	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.2430463149			Aug 27 05:36:42 AM UTC 24	Aug 27 05:56:20 AM UTC 24	325668817702 ps
T435	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.2818791853			Aug 27 05:56:21 AM UTC 24	Aug 27 05:56:25 AM UTC 24	2998190586 ps
T269	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.186411344			Aug 27 05:52:59 AM UTC 24	Aug 27 05:56:26 AM UTC 24	499283572585 ps
T283	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.888238218			Aug 27 05:56:05 AM UTC 24	Aug 27 05:56:34 AM UTC 24	166832152682 ps
T51	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1836936924			Aug 27 05:56:35 AM UTC 24	Aug 27 05:56:46 AM UTC 24	9234028546 ps
T436	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.678434503			Aug 27 05:55:28 AM UTC 24	Aug 27 05:56:51 AM UTC 24	164620686530 ps
T437	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.684155088			Aug 27 05:56:51 AM UTC 24	Aug 27 05:56:53 AM UTC 24	338413087 ps
T438	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.788369509			Aug 27 05:56:54 AM UTC 24	Aug 27 05:57:03 AM UTC 24	5964574905 ps
T235	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.1540374882			Aug 27 05:48:18 AM UTC 24	Aug 27 05:57:10 AM UTC 24	117538160443 ps
T439	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1874460278			Aug 27 05:54:09 AM UTC 24	Aug 27 05:57:17 AM UTC 24	410982570913 ps
T440	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.1991843488			Aug 27 05:56:26 AM UTC 24	Aug 27 05:57:19 AM UTC 24	33307841329 ps
T286	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.3688000944			Aug 27 05:36:58 AM UTC 24	Aug 27 05:57:22 AM UTC 24	489848094980 ps
T164	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.2464277264			Aug 27 05:50:16 AM UTC 24	Aug 27 05:57:27 AM UTC 24	254128930529 ps
T315	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.4044590668			Aug 27 05:49:55 AM UTC 24	Aug 27 05:57:33 AM UTC 24	202033643167 ps
T242	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.3266083317			Aug 27 05:36:45 AM UTC 24	Aug 27 05:57:38 AM UTC 24	492475472222 ps
T165	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.2923041608			Aug 27 05:54:11 AM UTC 24	Aug 27 05:57:42 AM UTC 24	485112733463 ps
T255	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.4118945863			Aug 27 05:47:48 AM UTC 24	Aug 27 05:57:49 AM UTC 24	346815624670 ps
T441	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.3239738797			Aug 27 05:57:43 AM UTC 24	Aug 27 05:57:51 AM UTC 24	5454139530 ps
T290	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.3738821589			Aug 27 05:40:31 AM UTC 24	Aug 27 05:57:53 AM UTC 24	406565755099 ps
T222	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.112433791			Aug 27 05:39:29 AM UTC 24	Aug 27 05:57:56 AM UTC 24	364949335348 ps
T442	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.4128678265			Aug 27 05:52:28 AM UTC 24	Aug 27 05:58:01 AM UTC 24	324360960376 ps
T281	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.2028825942			Aug 27 05:55:06 AM UTC 24	Aug 27 05:58:03 AM UTC 24	163549364181 ps
T443	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.1946967519			Aug 27 05:58:01 AM UTC 24	Aug 27 05:58:03 AM UTC 24	306266713 ps
T444	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.817875512			Aug 27 05:54:01 AM UTC 24	Aug 27 05:58:12 AM UTC 24	332607751205 ps
T445	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.1892386847			Aug 27 05:48:57 AM UTC 24	Aug 27 05:58:18 AM UTC 24	330946291164 ps
T446	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.2572377814			Aug 27 05:58:04 AM UTC 24	Aug 27 05:58:25 AM UTC 24	6066013964 ps
T447	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.1702959085			Aug 27 05:49:06 AM UTC 24	Aug 27 05:58:27 AM UTC 24	163943296472 ps
T33	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3341818994			Aug 27 05:57:53 AM UTC 24	Aug 27 05:58:35 AM UTC 24	5028633221 ps
T268	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.1677075149			Aug 27 05:48:46 AM UTC 24	Aug 27 05:58:46 AM UTC 24	354872972726 ps
T448	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.678046384			Aug 27 05:50:29 AM UTC 24	Aug 27 05:58:48 AM UTC 24	168286146061 ps
T251	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.3471111606			Aug 27 05:39:30 AM UTC 24	Aug 27 05:58:56 AM UTC 24	483423122789 ps
T449	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.1203336295			Aug 27 05:53:58 AM UTC 24	Aug 27 05:58:58 AM UTC 24	494265897149 ps
T282	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.193829937			Aug 27 05:45:23 AM UTC 24	Aug 27 05:59:06 AM UTC 24	327521413954 ps
T450	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.2666975310			Aug 27 05:58:57 AM UTC 24	Aug 27 05:59:08 AM UTC 24	4584865762 ps
T172	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.491741461			Aug 27 05:49:27 AM UTC 24	Aug 27 05:59:14 AM UTC 24	576662674312 ps
T451	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1894379693			Aug 27 05:58:26 AM UTC 24	Aug 27 05:59:18 AM UTC 24	162744870757 ps
T452	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.792310750			Aug 27 05:59:18 AM UTC 24	Aug 27 05:59:21 AM UTC 24	314300902 ps
T34	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.421432490			Aug 27 05:59:09 AM UTC 24	Aug 27 05:59:24 AM UTC 24	3073178051 ps
T453	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.3209148472			Aug 27 05:59:22 AM UTC 24	Aug 27 05:59:30 AM UTC 24	5566122202 ps
T166	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.1167039064			Aug 27 05:54:20 AM UTC 24	Aug 27 05:59:31 AM UTC 24	336481704413 ps
T389	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.1249926896			Aug 27 05:51:37 AM UTC 24	Aug 27 05:59:40 AM UTC 24	111666079433 ps
T454	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3593731389			Aug 27 05:36:45 AM UTC 24	Aug 27 05:59:33 AM UTC 24	492561999242 ps
T455	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.2629624634			Aug 27 05:57:50 AM UTC 24	Aug 27 05:59:35 AM UTC 24	46195068992 ps
T206	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.2192349122			Aug 27 05:49:37 AM UTC 24	Aug 27 05:59:50 AM UTC 24	353373106482 ps
T456	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.990821105			Aug 27 05:46:57 AM UTC 24	Aug 27 06:00:23 AM UTC 24	332387736646 ps
T312	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.2232315299			Aug 27 05:52:23 AM UTC 24	Aug 27 06:00:28 AM UTC 24	166843157804 ps
T457	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.1089117929			Aug 27 06:00:28 AM UTC 24	Aug 27 06:00:31 AM UTC 24	4746138359 ps
T151	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.2351217263			Aug 27 05:51:09 AM UTC 24	Aug 27 06:00:34 AM UTC 24	490495476083 ps
T458	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3720516694			Aug 27 05:36:45 AM UTC 24	Aug 27 06:00:41 AM UTC 24	612084949663 ps
T173	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.3795412043			Aug 27 05:56:05 AM UTC 24	Aug 27 06:00:42 AM UTC 24	383397610759 ps
T459	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.4021195550			Aug 27 05:58:59 AM UTC 24	Aug 27 06:00:54 AM UTC 24	46954534857 ps
T362	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2675762922			Aug 27 06:00:42 AM UTC 24	Aug 27 06:00:54 AM UTC 24	2311551546 ps
T460	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.3951066884			Aug 27 06:00:54 AM UTC 24	Aug 27 06:00:57 AM UTC 24	298335810 ps
T461	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.2167008485			Aug 27 06:00:54 AM UTC 24	Aug 27 06:01:04 AM UTC 24	5684060542 ps
T462	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled_fixed.2432054247			Aug 27 05:59:30 AM UTC 24	Aug 27 06:01:12 AM UTC 24	163284198721 ps
T288	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.48885125			Aug 27 05:57:23 AM UTC 24	Aug 27 06:01:13 AM UTC 24	183536084449 ps
T224	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.2882334334			Aug 27 05:50:10 AM UTC 24	Aug 27 06:01:16 AM UTC 24	93053865202 ps
T152	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.1410152636			Aug 27 05:38:23 AM UTC 24	Aug 27 06:01:18 AM UTC 24	493367702232 ps
T322	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.2910958191			Aug 27 05:50:56 AM UTC 24	Aug 27 06:01:24 AM UTC 24	367782422724 ps
T463	/workspaces/repo/scratch/os_regression_2024_08_26/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.3147469945			Aug 27 05:36:45 AM UTC 24	Aug 27 06:01:27 AM UTC 24	493959438663 ps