Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23324

1

T4

20

T5

14

T6

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19951

1

T4

20

T5

14

T6

2

auto[ADC_CTRL_FILTER_COND_OUT]

3373

1

T12

1

T14

2

T15

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17357

1

T4

20

T5

14

T6

2

auto[1]

5967

1

T14

2

T16

10

T18

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19611

1

T4

20

T5

14

T6

2

auto[1]

3713

1

T12

3

T14

2

T16

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	390	1			T15	2		T47	1		T138	1
values[1]	542	1			T22	23		T168	21		T236	1
values[2]	598	1			T14	2		T67	25		T160	2
values[3]	687	1			T68	25		T156	3		T237	21
values[4]	668	1			T20	13		T67	5		T62	2
values[5]	706	1			T6	2		T54	9		T238	11
values[6]	703	1			T18	27		T20	7		T239	1
values[7]	761	1			T12	1		T17	11		T137	25
values[8]	661	1			T17	12		T21	10		T68	16
values[9]	3104	1			T16	10		T19	2		T20	3
minimum	14504	1			T4	20		T5	14		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	652	1			T67	24		T168	21		T156	15
values[1]	533	1			T14	2		T67	1		T160	2
values[2]	757	1			T20	13		T68	25		T156	3
values[3]	597	1			T67	5		T62	2		T145	3
values[4]	653	1			T6	2		T239	1		T161	1
values[5]	878	1			T18	27		T20	7		T137	11
values[6]	2843	1			T12	1		T17	11		T23	15
values[7]	747	1			T16	10		T17	12		T19	2
values[8]	920	1			T15	2		T20	3		T84	5
values[9]	118	1			T157	23		T138	1		T240	1
minimum	14626	1			T4	20		T5	14		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

4255

1

T15

1

T18

16

T19

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T241	1		T163	1		T242	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T67	11		T168	11		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T67	1		T160	2		T52	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	2		T84	5		T141	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T20	1		T237	12		T42	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T68	11		T156	1		T243	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T62	2		T145	1		T54	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T67	3		T244	16		T245	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T6	2		T239	1		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T161	1		T197	1		T185	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T18	17		T149	10		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T20	1		T137	11		T247	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1667	1			T23	15		T68	8		T96	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	1		T17	1		T137	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T17	1		T19	2		T21	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T16	1		T136	10		T248	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T249	1		T196	14		T250	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T15	2		T20	1		T84	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T251	1		T252	1		T253	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T157	12		T138	1		T240	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14426	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T22	12		T236	1		T254	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T241	7		T255	3		T256	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T67	13		T168	10		T156	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T52	1		T257	10		T164	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T84	14		T258	3		T259	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T20	12		T237	9		T42	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T68	14		T156	2		T243	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T145	2		T42	15		T238	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T67	2		T244	14		T222	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T185	7		T171	1		T158	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T185	17		T260	16		T152	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T18	10		T149	10		T201	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T20	6		T248	9		T202	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	831	1			T68	8		T159	10		T144	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T17	10		T149	4		T261	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T17	11		T21	2		T145	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T16	9		T136	6		T248	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T196	3		T250	9		T163	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T20	2		T84	2		T262	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T253	5		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T157	11		T263	7		T264	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T12	3		T14	2		T97	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T22	11		T254	11		T155	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T196	1		T250	9		T163	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T15	2		T47	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T163	1		T242	1		T251	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T22	12		T168	11		T236	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T67	1		T160	2		T52	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T14	2		T67	11		T84	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T237	12		T140	7		T265	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T68	11		T156	1		T243	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T20	1		T62	2		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T67	3		T244	16		T265	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	2		T54	9		T238	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T161	1		T197	1		T185	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T18	17		T239	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T20	1		T247	11		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T146	2		T140	14		T149	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T12	1		T17	1		T137	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T17	1		T21	8		T68	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T136	10		T149	6		T266	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1806	1			T19	2		T23	15		T96	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T16	1		T20	1		T84	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14409	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T196	1		T250	9		T163	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T255	13		T173	7		T207	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T256	15		T267	11		T110	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T22	11		T168	10		T151	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T52	1		T257	10		T241	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T67	13		T84	14		T156	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T237	9		T242	8		T268	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T68	14		T156	2		T243	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T20	12		T145	2		T42	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T67	2		T244	14		T206	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T238	4		T139	5		T185	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T185	17		T260	10		T222	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T18	10		T201	8		T269	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T20	6		T260	6		T248	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T149	10		T244	2		T270	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T17	10		T261	10		T212	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T17	11		T21	2		T68	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T136	6		T149	4		T266	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	934	1			T159	10		T144	20		T55	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	9		T20	2		T84	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T241	8		T163	1		T242	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T67	14		T168	11		T156	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T67	1		T160	2		T52	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	2		T84	15		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T20	13		T237	10		T42	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T68	15		T156	3		T243	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T62	2		T145	3		T54	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T67	3		T244	15		T245	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	2		T239	1		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T161	1		T197	1		T185	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T18	11		T149	11		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T20	7		T137	1		T247	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1160	1			T23	1		T68	9		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	1		T17	11		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T17	12		T19	1		T21	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T16	10		T136	7		T248	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T249	1		T196	5		T250	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T15	1		T20	3		T84	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T251	1		T252	1		T253	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T157	12		T138	1		T240	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14526	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T22	12		T236	1		T254	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T271	8		T267	5		T272	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T67	10		T168	10		T201	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T46	14		T140	6		T257	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T84	4		T141	2		T142	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T237	11		T42	8		T139	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T68	10		T162	12		T166	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T54	8		T42	11		T238	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T67	2		T244	15		T245	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T185	7		T158	12		T201	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T185	18		T142	2		T260	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T18	16		T149	9		T201	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T137	10		T247	10		T248	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T23	14		T68	7		T96	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T137	13		T149	5		T261	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T19	1		T21	7		T52	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T136	9		T248	5		T273	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T196	12		T250	8		T162	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	1		T84	2		T140	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T253	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T157	11		T274	10		T263	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T110	11		T275	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T22	11		T254	12		T276	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T196	2		T250	10		T163	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T15	1		T47	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T163	1		T242	1		T251	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T22	12		T168	11		T236	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T67	1		T160	2		T52	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	2		T67	14		T84	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T237	10		T140	1		T265	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T68	15		T156	3		T243	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T20	13		T62	2		T145	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T67	3		T244	15		T265	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	2		T54	1		T238	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T161	1		T197	1		T185	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T18	11		T239	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T20	7		T247	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T146	2		T140	1		T149	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	1		T17	11		T137	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T17	12		T21	3		T68	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T136	7		T149	5		T266	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T19	1		T23	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T16	10		T20	3		T84	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14504	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T250	8		T163	12		T277	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T15	1		T140	11		T255	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T271	8		T267	5		T110	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T22	11		T168	10		T172	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T46	14		T257	9		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T67	10		T84	4		T141	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T237	11		T140	6		T265	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T68	10		T142	16		T162	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T42	19		T139	14		T141	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T67	2		T244	15		T265	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T54	8		T238	6		T139	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T185	18		T142	2		T260	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T18	16		T201	6		T269	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T247	10		T260	6		T248	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T140	13		T149	9		T244	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T137	23		T261	14		T212	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T21	7		T68	7		T52	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T136	9		T149	5		T172	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1463	1			T19	1		T23	14		T96	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T84	2		T157	11		T248	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

auto[0]

4255

1

T15

1

T18

16

T19

1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23324

1

T4

20

T5

14

T6

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19851

1

T4

20

T5

14

T6

2

auto[ADC_CTRL_FILTER_COND_OUT]

3473

1

T17

12

T19

2

T20

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17186

1

T4

20

T5

14

T6

2

auto[1]

6138

1

T12

2

T60

1

T14

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19611

1

T4

20

T5

14

T6

2

auto[1]

3713

1

T12

3

T14

2

T16

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	319	1			T12	1		T60	1		T14	1
values[0]	79	1			T177	1		T278	1		T210	24
values[1]	485	1			T14	2		T15	2		T17	11
values[2]	2978	1			T18	27		T23	15		T96	11
values[3]	708	1			T12	1		T22	23		T62	2
values[4]	479	1			T68	25		T160	1		T161	1
values[5]	585	1			T16	10		T67	24		T84	19
values[6]	872	1			T67	6		T52	28		T54	9
values[7]	545	1			T20	7		T68	16		T237	21
values[8]	695	1			T17	12		T21	10		T46	15
values[9]	1383	1			T6	2		T19	2		T20	16
minimum	14196	1			T4	20		T5	14		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	773	1			T14	2		T15	2		T17	11
values[1]	3023	1			T12	1		T18	27		T23	15
values[2]	656	1			T22	23		T160	1		T145	10
values[3]	334	1			T68	25		T84	19		T148	1
values[4]	749	1			T16	10		T67	24		T42	27
values[5]	888	1			T67	6		T68	16		T145	3
values[6]	437	1			T20	7		T237	21		T46	15
values[7]	740	1			T17	12		T137	25		T148	1
values[8]	1006	1			T19	2		T20	16		T21	10
values[9]	214	1			T6	2		T84	5		T136	16
minimum	14504	1			T4	20		T5	14		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

4255

1

T15

1

T18

16

T19

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T14	2		T15	2		T17	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T249	1		T146	2		T279	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1695	1			T12	1		T18	17		T23	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T140	14		T244	16		T270	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T22	12		T162	13		T269	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T160	1		T145	1		T52	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T84	5		T150	1		T260	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T68	11		T148	1		T197	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T16	1		T67	11		T247	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T42	12		T150	1		T185	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T67	3		T145	1		T54	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T67	1		T68	8		T52	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T47	1		T142	3		T280	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T20	1		T237	12		T46	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T137	11		T148	1		T240	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T17	1		T137	14		T149	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T21	8		T236	1		T248	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T19	2		T20	2		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T6	2		T84	3		T136	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T64	1		T196	1		T250	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14409	1			T4	20		T5	14		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T17	10		T168	10		T165	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T242	8		T255	13		T281	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T18	10		T159	10		T144	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T244	14		T270	1		T201	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T22	11		T269	11		T282	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T145	9		T52	1		T171	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T84	14		T150	14		T260	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T68	14		T202	10		T268	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T16	9		T67	13		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T42	15		T185	7		T151	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T67	2		T145	2		T196	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T68	8		T52	15		T261	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T283	1		T282	13		T284	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T20	6		T237	9		T238	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T152	6		T277	6		T273	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T17	11		T149	10		T248	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T21	2		T248	4		T255	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T20	14		T156	16		T139	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T84	2		T136	6		T257	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T196	1		T250	9		T244	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1