Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23324

1

T4

20

T5

14

T6

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19735

1

T4

20

T5

14

T7

20

auto[ADC_CTRL_FILTER_COND_OUT]

3589

1

T6

2

T12

1

T15

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17549

1

T4

20

T5

14

T6

2

auto[1]

5775

1

T15

2

T16

10

T17

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19611

1

T4

20

T5

14

T6

2

auto[1]

3713

1

T12

3

T14

2

T16

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	187	1			T156	3		T247	11		T266	12
values[0]	36	1			T297	1		T110	6		T313	29
values[1]	697	1			T18	27		T67	1		T47	1
values[2]	760	1			T17	12		T22	23		T84	5
values[3]	633	1			T62	2		T162	12		T241	8
values[4]	718	1			T14	2		T19	2		T54	9
values[5]	728	1			T6	2		T16	10		T17	11
values[6]	750	1			T249	1		T196	2		T150	1
values[7]	665	1			T67	5		T68	25		T160	1
values[8]	2892	1			T21	10		T23	15		T96	11
values[9]	754	1			T12	1		T15	2		T20	20
minimum	14504	1			T4	20		T5	14		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	535	1			T18	27		T67	1		T239	1
values[1]	776	1			T17	12		T22	23		T84	5
values[2]	622	1			T62	2		T148	1		T150	1
values[3]	796	1			T14	2		T19	2		T67	24
values[4]	689	1			T6	2		T16	10		T17	11
values[5]	761	1			T67	5		T156	15		T249	1
values[6]	2821	1			T23	15		T68	25		T96	11
values[7]	799	1			T20	7		T21	10		T52	2
values[8]	684	1			T12	1		T15	2		T20	13
values[9]	15	1			T163	1		T269	2		T352	1
minimum	14826	1			T4	20		T5	14		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

4255

1

T15

1

T18

16

T19

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T18	17		T246	1		T139	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T67	1		T239	1		T196	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T22	12		T84	3		T42	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T17	1		T52	13		T257	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T148	1		T150	1		T250	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T62	2		T241	1		T201	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	2		T19	2		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T67	11		T54	9		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T17	1		T20	1		T157	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	2		T16	1		T68	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T156	1		T249	1		T64	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T67	3		T149	10		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1657	1			T23	15		T96	11		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T68	11		T160	1		T84	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T20	1		T52	1		T238	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T21	8		T138	1		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T168	11		T156	1		T42	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	1		T15	2		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T163	1		T353	1		T80	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T269	1		T352	1		T354	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14435	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T47	1		T137	14		T146	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T18	10		T139	5		T261	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T196	2		T171	1		T260	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T22	11		T84	2		T42	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T17	11		T52	15		T257	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T250	9		T201	14		T202	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T241	7		T201	8		T165	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T145	9		T243	2		T270	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T67	13		T139	10		T158	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T17	10		T20	2		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T16	9		T68	8		T149	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T156	14		T196	1		T151	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T67	2		T149	10		T185	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	867	1			T159	10		T144	20		T55	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T68	14		T84	14		T237	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T20	6		T52	1		T238	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T21	2		T244	14		T262	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T168	10		T156	2		T42	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T20	12		T136	6		T145	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T80	1		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T269	1		T354	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T12	3		T14	2		T97	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T212	9		T269	16		T154	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T156	1		T247	11		T269	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T266	1		T352	1		T155	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T297	1		T110	5		T313	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T18	17		T246	1		T261	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T67	1		T47	1		T137	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T22	12		T84	3		T42	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T17	1		T52	13		T257	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T162	12		T201	16		T248	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T62	2		T241	1		T201	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	2		T19	2		T137	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T54	9		T161	1		T139	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T17	1		T20	1		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	2		T16	1		T67	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T249	1		T196	1		T222	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T150	1		T185	19		T257	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T156	1		T64	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T67	3		T68	11		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1641	1			T23	15		T96	11		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T21	8		T138	1		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T20	1		T168	11		T42	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	1		T15	2		T20	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14409	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T156	2		T269	11		T259	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T266	11		T155	9		T354	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T110	1		T313	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T18	10		T261	10		T201	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T196	2		T171	1		T212	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T22	11		T84	2		T42	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T17	11		T52	15		T257	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T201	14		T248	4		T202	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T241	7		T201	8		T151	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T270	1		T202	10		T163	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T139	10		T165	1		T151	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T17	10		T20	2		T145	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T16	9		T67	13		T68	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T196	1		T222	18		T151	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T185	17		T257	7		T242	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T156	14		T290	13		T153	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T67	2		T68	14		T84	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	893	1			T159	10		T144	20		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T21	2		T244	14		T262	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T20	6		T168	10		T42	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T20	12		T136	6		T145	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T18	11		T246	1		T139	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T67	1		T239	1		T196	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T22	12		T84	3		T42	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T17	12		T52	16		T257	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T148	1		T150	1		T250	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T62	2		T241	8		T201	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T14	2		T19	1		T145	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T67	14		T54	1		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T17	11		T20	3		T157	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	2		T16	10		T68	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T156	15		T249	1		T64	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T67	3		T149	11		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1194	1			T23	1		T96	1		T159	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T68	15		T160	1		T84	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T20	7		T52	2		T238	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T21	3		T138	1		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T168	11		T156	3		T42	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	1		T15	1		T20	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T163	1		T353	1		T80	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T269	2		T352	1		T354	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14529	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T47	1		T137	1		T146	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T18	16		T139	2		T261	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T196	12		T260	6		T162	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T22	11		T84	2		T42	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T52	12		T257	9		T151	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T250	8		T162	11		T201	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T201	6		T277	11		T267	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T19	1		T137	10		T270	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T67	10		T54	8		T139	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T157	11		T140	11		T260	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T68	7		T46	14		T140	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T172	11		T151	11		T271	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T67	2		T149	9		T185	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T23	14		T96	10		T49	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T68	10		T84	4		T237	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T238	6		T315	13		T290	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T21	7		T140	6		T244	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T168	10		T42	11		T247	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T15	1		T136	9		T245	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T80	1		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T354	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T141	15		T187	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T137	13		T212	12		T269	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T156	3		T247	1		T269	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T266	12		T352	1		T155	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T297	1		T110	2		T313	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T18	11		T246	1		T261	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T67	1		T47	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T22	12		T84	3		T42	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T17	12		T52	16		T257	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T162	1		T201	15		T248	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T62	2		T241	8		T201	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T14	2		T19	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T54	1		T161	1		T139	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T17	11		T20	3		T145	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	2		T16	10		T67	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T249	1		T196	2		T222	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T150	1		T185	18		T257	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T156	15		T64	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T67	3		T68	15		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1223	1			T23	1		T96	1		T159	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T21	3		T138	1		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T20	7		T168	11		T42	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T12	1		T15	1		T20	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14504	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T247	10		T269	10		T355	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T354	1		T356	12		T357	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T110	4		T313	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T18	16		T261	14		T141	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T137	13		T196	12		T212	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T22	11		T84	2		T42	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T52	12		T257	9		T277	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T162	11		T201	15		T248	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T201	6		T151	6		T277	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T19	1		T137	10		T270	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T54	8		T139	14		T151	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T157	11		T140	11		T260	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T67	10		T68	7		T46	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T222	12		T172	11		T151	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T185	18		T257	3		T166	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T290	13		T153	6		T347	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T67	2		T68	10		T84	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T23	14		T96	10		T49	32
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T21	7		T140	6		T244	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T168	10		T42	11		T320	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T15	1		T136	9		T142	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

auto[0]

4255

1

T15

1

T18

16

T19

1