Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23324

1

T4

20

T5

14

T6

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19779

1

T4

20

T5

14

T7

20

auto[ADC_CTRL_FILTER_COND_OUT]

3545

1

T6

2

T12

1

T15

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17713

1

T4

20

T5

14

T6

2

auto[1]

5611

1

T15

2

T16

10

T17

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19611

1

T4

20

T5

14

T6

2

auto[1]

3713

1

T12

3

T14

2

T16

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T343	1		T352	1		T355	12
values[0]	128	1			T212	22		T141	16		T201	39
values[1]	635	1			T18	27		T67	1		T47	1
values[2]	720	1			T17	12		T22	23		T84	5
values[3]	614	1			T62	2		T42	18		T162	12
values[4]	763	1			T14	2		T54	9		T137	11
values[5]	754	1			T6	2		T16	10		T17	11
values[6]	701	1			T249	1		T196	2		T150	1
values[7]	688	1			T67	5		T68	25		T160	1
values[8]	2838	1			T21	10		T23	15		T96	11
values[9]	965	1			T12	1		T15	2		T20	20
minimum	14504	1			T4	20		T5	14		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	830	1			T18	27		T22	23		T67	1
values[1]	724	1			T17	12		T52	28		T42	18
values[2]	623	1			T148	1		T150	1		T250	18
values[3]	792	1			T14	2		T19	2		T67	24
values[4]	755	1			T6	2		T16	10		T17	11
values[5]	634	1			T67	5		T249	1		T64	1
values[6]	2908	1			T23	15		T68	25		T96	11
values[7]	759	1			T20	7		T21	10		T52	2
values[8]	720	1			T12	1		T15	2		T20	13
values[9]	18	1			T163	1		T269	2		T352	1
minimum	14561	1			T4	20		T5	14		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

4255

1

T15

1

T18

16

T19

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T18	17		T22	12		T84	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T67	1		T47	1		T239	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T42	9		T248	6		T245	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T17	1		T52	13		T257	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T148	1		T150	1		T250	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T241	1		T201	23		T286	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	2		T19	2		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T67	11		T62	2		T54	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T17	1		T20	1		T157	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	2		T16	1		T68	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T249	1		T64	1		T196	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T67	3		T150	1		T257	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1710	1			T23	15		T96	11		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T68	11		T160	1		T84	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T20	1		T52	1		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T21	8		T138	1		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T168	11		T156	1		T42	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	1		T15	2		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T163	1		T353	1		T358	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T269	1		T352	1		T359	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14412	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T137	14		T171	2		T212	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T18	10		T22	11		T84	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T196	2		T260	6		T269	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T42	9		T248	4		T311	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T17	11		T52	15		T257	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T250	9		T202	16		T254	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T241	7		T201	22		T165	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T145	9		T270	1		T163	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T67	13		T139	10		T281	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T17	10		T20	2		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T16	9		T68	8		T149	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T196	1		T151	11		T256	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T67	2		T257	7		T164	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	926	1			T159	10		T144	20		T156	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T68	14		T84	14		T237	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T20	6		T52	1		T196	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T21	2		T244	14		T262	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T168	10		T156	2		T42	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T20	12		T136	6		T145	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T358	1		T80	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T269	1		T354	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T171	1		T212	9		T349	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T355	12		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T343	1		T352	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T201	21		T297	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T212	13		T141	16		T360	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T18	17		T246	1		T261	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T67	1		T47	1		T137	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T22	12		T84	3		T139	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T17	1		T52	13		T162	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T42	9		T162	12		T248	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T62	2		T241	1		T201	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T14	2		T137	11		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T54	9		T139	15		T240	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T17	1		T19	2		T20	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	2		T16	1		T67	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T249	1		T196	1		T185	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T150	1		T257	4		T282	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T156	1		T64	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T67	3		T68	11		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1655	1			T23	15		T96	11		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T21	8		T237	12		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T20	1		T168	11		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T12	1		T15	2		T20	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14409	1			T4	20		T5	14		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T201	18		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T212	9		T360	4		T210	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T18	10		T261	10		T248	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T196	2		T171	1		T260	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T22	11		T84	2		T139	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	11		T52	15		T312	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T42	9		T248	4		T202	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T241	7		T201	22		T151	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T270	1		T202	10		T163	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T139	10		T165	1		T281	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T17	10		T20	2		T145	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T16	9		T67	13		T68	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T196	1		T185	17		T222	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T257	7		T282	1		T166	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T156	14		T290	13		T153	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T67	2		T68	14		T84	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	900	1			T159	10		T144	20		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T21	2		T237	9		T244	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T20	6		T168	10		T156	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T20	12		T136	6		T145	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T18	11		T22	12		T84	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T67	1		T47	1		T239	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T42	10		T248	5		T245	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T17	12		T52	16		T257	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T148	1		T150	1		T250	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T241	8		T201	24		T286	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	2		T19	1		T145	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T67	14		T62	2		T54	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T17	11		T20	3		T157	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	2		T16	10		T68	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T249	1		T64	1		T196	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T67	3		T150	1		T257	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T23	1		T96	1		T159	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T68	15		T160	1		T84	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T20	7		T52	2		T196	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T21	3		T138	1		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T168	11		T156	3		T42	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	1		T15	1		T20	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T163	1		T353	1		T358	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T269	2		T352	1		T359	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14505	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T137	1		T171	3		T212	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T18	16		T22	11		T84	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T196	12		T141	15		T260	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T42	8		T248	5		T245	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T52	12		T257	9		T151	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T250	8		T162	11		T265	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T201	21		T151	7		T277	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T19	1		T137	10		T270	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T67	10		T54	8		T139	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T157	11		T140	11		T260	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T68	7		T46	14		T140	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T172	11		T151	11		T337	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T67	2		T257	3		T164	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T23	14		T96	10		T49	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T68	10		T84	4		T237	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T315	13		T255	11		T172	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T21	7		T140	6		T244	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T168	10		T42	11		T238	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	1		T136	9		T245	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T80	1		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T354	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T361	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T137	13		T212	12		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T355	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T343	1		T352	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T201	19		T297	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T212	10		T141	1		T360	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T18	11		T246	1		T261	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T67	1		T47	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T22	12		T84	3		T139	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T17	12		T52	16		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T42	10		T162	1		T248	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T62	2		T241	8		T201	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T14	2		T137	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T54	1		T139	11		T240	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T17	11		T19	1		T20	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T6	2		T16	10		T67	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T249	1		T196	2		T185	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T150	1		T257	8		T282	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T156	15		T64	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T67	3		T68	15		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T23	1		T96	1		T159	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T21	3		T237	10		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T20	7		T168	11		T156	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T12	1		T15	1		T20	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14504	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T355	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T201	20		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T212	12		T141	15		T210	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T18	16		T261	14		T141	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T137	13		T196	12		T260	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T22	11		T84	2		T139	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T52	12		T162	12		T277	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T42	8		T162	11		T248	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T201	21		T151	6		T277	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T137	10		T270	1		T245	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T54	8		T139	14		T151	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T19	1		T157	11		T140	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T67	10		T68	7		T46	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T185	18		T222	12		T151	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T257	3		T166	9		T308	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T290	13		T172	11		T153	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T67	2		T68	10		T84	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T23	14		T96	10		T49	32
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T21	7		T237	11		T140	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T168	10		T42	11		T247	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	1		T136	9		T142	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

auto[0]

4255

1

T15

1

T18

16

T19

1