Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23324

1

T4

20

T5

14

T6

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20179

1

T4

20

T5

14

T7

20

auto[ADC_CTRL_FILTER_COND_OUT]

3145

1

T6

2

T12

1

T15

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17612

1

T4

20

T5

14

T6

2

auto[1]

5712

1

T14

2

T16

10

T17

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19611

1

T4

20

T5

14

T6

2

auto[1]

3713

1

T12

3

T14

2

T16

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	202	1			T17	11		T139	8		T212	22
values[0]	34	1			T312	7		T343	1		T347	14
values[1]	787	1			T15	2		T22	23		T62	2
values[2]	629	1			T14	2		T17	12		T20	7
values[3]	837	1			T12	1		T84	24		T145	10
values[4]	510	1			T20	13		T68	16		T145	3
values[5]	2797	1			T16	10		T23	15		T96	11
values[6]	772	1			T54	9		T64	1		T140	21
values[7]	716	1			T20	3		T21	10		T67	24
values[8]	629	1			T6	2		T19	2		T67	1
values[9]	907	1			T18	27		T237	21		T47	1
minimum	14504	1			T4	20		T5	14		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	809	1			T15	2		T67	5		T42	27
values[1]	608	1			T12	1		T14	2		T17	12
values[2]	789	1			T68	16		T84	24		T145	3
values[3]	2731	1			T20	13		T23	15		T96	11
values[4]	607	1			T16	10		T52	2		T46	15
values[5]	769	1			T156	3		T54	9		T139	25
values[6]	711	1			T6	2		T20	3		T21	10
values[7]	728	1			T19	2		T136	16		T237	21
values[8]	687	1			T17	11		T18	27		T47	1
values[9]	155	1			T139	8		T149	10		T165	3
minimum	14730	1			T4	20		T5	14		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

4255

1

T15

1

T18

16

T19

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T67	3		T42	12		T202	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T15	2		T249	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T14	2		T247	11		T146	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	1		T17	1		T20	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T68	8		T84	8		T52	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T145	1		T150	1		T171	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1712	1			T20	1		T23	15		T96	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T150	1		T315	14		T362	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T16	1		T52	1		T157	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T46	15		T137	11		T64	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T156	1		T54	9		T139	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T140	7		T261	15		T244	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T20	1		T21	8		T67	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T6	2		T67	1		T68	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T237	12		T137	14		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T19	2		T136	10		T239	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T17	1		T18	17		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T47	1		T148	1		T212	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T139	3		T149	6		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T165	2		T328	9		T302	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14495	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T152	1		T347	14		T259	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T67	2		T42	15		T202	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T201	18		T166	19		T312	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T196	2		T260	10		T201	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T17	11		T20	6		T145	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T68	8		T84	16		T52	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T145	2		T171	1		T262	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	891	1			T20	12		T159	10		T144	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T315	20		T345	8		T363	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T16	9		T52	1		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T196	1		T270	1		T163	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T156	2		T139	10		T150	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T261	10		T244	14		T290	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T20	2		T21	2		T67	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T68	14		T257	10		T248	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T237	9		T266	11		T283	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T136	6		T196	1		T243	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T17	10		T18	10		T244	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T212	9		T241	7		T201	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T139	5		T149	4		T166	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T165	1		T328	9		T302	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	3		T14	2		T97	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T152	13		T259	12		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T17	1		T139	3		T364	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T212	13		T165	2		T268	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T343	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T312	1		T347	14		T203	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T22	12		T62	2		T42	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	2		T249	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T14	2		T67	3		T247	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T17	1		T20	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T84	8		T52	13		T42	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	1		T145	1		T149	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T20	1		T68	8		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T145	1		T150	1		T315	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1635	1			T16	1		T23	15		T96	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T46	15		T137	11		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T54	9		T140	14		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T64	1		T140	7		T261	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T20	1		T21	8		T67	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T257	10		T268	10		T172	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T156	1		T137	14		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	2		T19	2		T67	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T18	17		T237	12		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T47	1		T239	1		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14409	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T17	10		T139	5		T364	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T212	9		T165	1		T344	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T312	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T22	11		T42	15		T238	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T201	18		T151	11		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T67	2		T260	10		T202	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T17	11		T20	6		T185	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T84	16		T52	15		T42	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T145	9		T149	10		T171	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T20	12		T68	8		T248	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T145	2		T315	20		T331	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	884	1			T16	9		T159	10		T144	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T196	1		T270	1		T163	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T150	14		T269	11		T165	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T261	10		T244	14		T248	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T20	2		T21	2		T67	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T257	10		T268	2		T323	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T156	14		T283	1		T173	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T68	14		T136	6		T196	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T18	10		T237	9		T149	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T241	7		T201	14		T328	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T67	3		T42	16		T202	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T15	1		T249	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T14	2		T247	1		T146	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	1		T17	12		T20	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T68	9		T84	18		T52	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T145	3		T150	1		T171	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T20	13		T23	1		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T150	1		T315	21		T362	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T16	10		T52	2		T157	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T46	1		T137	1		T64	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T156	3		T54	1		T139	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T140	1		T261	11		T244	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T20	3		T21	3		T67	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	2		T67	1		T68	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T237	10		T137	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T19	1		T136	7		T239	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T17	11		T18	11		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T47	1		T148	1		T212	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T139	6		T149	5		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T165	2		T328	10		T302	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14584	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T152	14		T347	1		T259	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T67	2		T42	11		T265	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T15	1		T142	16		T201	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T247	10		T196	12		T260	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T149	9		T185	7		T245	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T68	7		T84	6		T52	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T141	15		T151	6		T308	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T23	14		T96	10		T49	32
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T315	13		T345	5		T363	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T157	11		T140	13		T269	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T46	14		T137	10		T270	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T54	8		T139	14		T162	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T140	6		T261	14		T244	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T21	7		T67	10		T168	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T68	10		T257	9		T248	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T237	11		T137	13		T173	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T19	1		T136	9		T250	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T18	16		T140	11		T244	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T212	12		T201	15		T245	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T139	2		T149	5		T166	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T165	1		T328	8		T302	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T22	11		T238	6		T248	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T347	13		T259	13		T203	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T17	11		T139	6		T364	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T212	10		T165	2		T268	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T343	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T312	7		T347	1		T203	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T22	12		T62	2		T42	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T15	1		T249	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T14	2		T67	3		T247	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T17	12		T20	7		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T84	18		T52	16		T42	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T12	1		T145	10		T149	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T20	13		T68	9		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T145	3		T150	1		T315	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T16	10		T23	1		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T46	1		T137	1		T196	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T54	1		T140	1		T150	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T64	1		T140	1		T261	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T20	3		T21	3		T67	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T257	11		T268	3		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T156	15		T137	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T6	2		T19	1		T67	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T18	11		T237	10		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T47	1		T239	1		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14504	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T139	2		T365	6		T363	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T212	12		T165	1		T178	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T347	13		T203	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T22	11		T42	11		T238	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	1		T142	16		T201	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T67	2		T247	10		T260	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T185	7		T166	21		T327	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T84	6		T52	12		T42	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T149	9		T141	15		T245	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T68	7		T248	5		T265	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T315	13		T308	7		T331	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T23	14		T96	10		T49	32
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T46	14		T137	10		T270	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T54	8		T140	13		T162	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T140	6		T261	14		T244	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T21	7		T67	10		T168	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T257	9		T268	9		T172	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T137	13		T173	11		T271	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T19	1		T68	10		T136	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T18	16		T237	11		T140	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T201	15		T245	15		T322	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

auto[0]

4255

1

T15

1

T18

16

T19

1