Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23324

1

T4

20

T5

14

T6

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20020

1

T4

20

T5

14

T6

2

auto[ADC_CTRL_FILTER_COND_OUT]

3304

1

T14

2

T17

12

T18

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17249

1

T4

20

T5

14

T6

2

auto[1]

6075

1

T15

2

T16

10

T19

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19611

1

T4

20

T5

14

T6

2

auto[1]

3713

1

T12

3

T14

2

T16

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	38	1			T340	14		T338	24		-	-
values[0]	119	1			T160	1		T145	10		T42	27
values[1]	618	1			T6	2		T20	7		T84	19
values[2]	2921	1			T14	2		T23	15		T96	11
values[3]	752	1			T12	1		T16	10		T19	2
values[4]	474	1			T46	15		T137	11		T239	1
values[5]	580	1			T17	12		T22	23		T67	5
values[6]	592	1			T15	2		T136	16		T137	14
values[7]	537	1			T17	11		T20	3		T68	16
values[8]	627	1			T20	13		T67	25		T160	1
values[9]	1562	1			T18	27		T21	10		T68	25
minimum	14504	1			T4	20		T5	14		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	868	1			T6	2		T20	7		T160	1
values[1]	2928	1			T14	2		T19	2		T23	15
values[2]	659	1			T12	1		T16	10		T84	5
values[3]	601	1			T52	28		T42	18		T138	1
values[4]	520	1			T17	12		T22	23		T67	5
values[5]	631	1			T15	2		T20	3		T68	16
values[6]	569	1			T17	11		T168	21		T47	1
values[7]	525	1			T20	13		T67	25		T62	2
values[8]	1222	1			T18	27		T21	10		T68	25
values[9]	275	1			T154	17		T353	1		T331	24
minimum	14526	1			T4	20		T5	14		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

4255

1

T15

1

T18

16

T19

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T6	2		T20	1		T84	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T160	1		T42	12		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1663	1			T19	2		T23	15		T96	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T14	2		T156	2		T247	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	1		T16	1		T54	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T84	3		T46	15		T239	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T42	9		T138	1		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T52	13		T196	13		T260	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T22	12		T136	10		T141	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T17	1		T67	3		T244	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T15	2		T20	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T68	8		T137	14		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T17	1		T168	11		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T161	1		T245	9		T206	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T20	1		T67	11		T62	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T67	1		T246	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T238	7		T64	1		T139	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T18	17		T21	8		T68	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T154	7		T353	1		T370	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T331	13		T176	1		T340	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14409	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T188	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T20	6		T84	14		T145	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T42	15		T150	14		T185	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	879	1			T159	10		T144	20		T55	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T156	16		T317	11		T274	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T16	9		T201	8		T242	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T84	2		T269	27		T165	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T42	9		T260	6		T158	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T52	15		T196	2		T260	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T22	11		T136	6		T283	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T17	11		T67	2		T244	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T20	2		T196	1		T244	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T68	8		T248	9		T371	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T17	10		T168	10		T270	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T206	15		T153	6		T372	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T20	12		T67	13		T157	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T261	10		T315	20		T152	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T238	4		T139	10		T149	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T18	10		T21	2		T68	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T154	10		T373	9		T374	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T331	11		T340	13		T375	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T188	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T338	13		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T340	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T145	1		T254	13		T326	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T160	1		T42	12		T376	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	2		T20	1		T84	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T148	1		T140	12		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1715	1			T23	15		T96	11		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	2		T156	1		T247	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T12	1		T16	1		T19	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T84	3		T156	1		T240	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T137	11		T146	2		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T46	15		T239	1		T196	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T22	12		T42	9		T158	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T17	1		T67	3		T52	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T15	2		T136	10		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T137	14		T138	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T17	1		T20	1		T168	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T68	8		T245	9		T286	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T20	1		T67	11		T157	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T67	1		T160	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	467	1			T62	2		T238	7		T64	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T18	17		T21	8		T68	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14409	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T338	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T340	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T145	9		T254	11		T377	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T42	15		T378	1		T379	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T20	6		T84	14		T145	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T165	1		T290	13		T380	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	890	1			T159	10		T144	20		T55	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T156	2		T150	14		T185	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T16	9		T201	8		T242	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T84	2		T156	14		T269	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T260	6		T201	18		T281	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T196	2		T260	10		T257	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T22	11		T42	9		T158	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T17	11		T67	2		T52	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T136	6		T196	1		T244	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T248	9		T371	2		T287	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T17	10		T20	2		T168	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T68	8		T206	15		T208	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T20	12		T67	13		T157	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T261	10		T153	6		T372	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	387	1			T238	4		T139	10		T149	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T18	10		T21	2		T68	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T6	2		T20	7		T84	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T160	1		T42	16		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T19	1		T23	1		T96	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	2		T156	18		T247	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T12	1		T16	10		T54	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T84	3		T46	1		T239	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T42	10		T138	1		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T52	16		T196	3		T260	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	12		T136	7		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T17	12		T67	3		T244	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T15	1		T20	3		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T68	9		T137	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T17	11		T168	11		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T161	1		T245	1		T206	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T20	13		T67	14		T62	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T67	1		T246	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	386	1			T238	5		T64	1		T139	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T18	11		T21	3		T68	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T154	11		T353	1		T370	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T331	12		T176	1		T340	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14504	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T188	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T84	4		T149	9		T185	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T42	11		T140	11		T185	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T19	1		T23	14		T96	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T247	10		T265	11		T317	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T54	8		T137	10		T201	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T84	2		T46	14		T269	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T42	8		T260	6		T158	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T52	12		T196	12		T260	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T22	11		T136	9		T141	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T67	2		T244	15		T151	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T15	1		T244	4		T248	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T68	7		T137	13		T248	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T168	10		T270	1		T255	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T245	8		T206	4		T288	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T67	10		T157	11		T139	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T261	14		T141	2		T315	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T238	6		T139	14		T149	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T18	16		T21	7		T68	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T154	6		T370	9		T373	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T331	12		T375	9		T381	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T188	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T338	12		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T340	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T145	10		T254	12		T326	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T160	1		T42	16		T376	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	2		T20	7		T84	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T148	1		T140	1		T165	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1223	1			T23	1		T96	1		T159	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	2		T156	3		T247	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	1		T16	10		T19	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T84	3		T156	15		T240	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T137	1		T146	2		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T46	1		T239	1		T196	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T22	12		T42	10		T158	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T17	12		T67	3		T52	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T15	1		T136	7		T196	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T137	1		T138	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T17	11		T20	3		T168	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T68	9		T245	1		T286	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T20	13		T67	14		T157	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T67	1		T160	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	464	1			T62	2		T238	5		T64	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	406	1			T18	11		T21	3		T68	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14504	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T338	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T254	12		T326	9		T377	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T42	11		T378	13		T379	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T84	4		T149	9		T245	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T140	11		T290	13		T172	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T23	14		T96	10		T49	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T247	10		T185	7		T265	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T19	1		T54	8		T201	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T84	2		T269	24		T151	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T137	10		T260	6		T201	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T46	14		T196	12		T260	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T22	11		T42	8		T158	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T67	2		T52	12		T244	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T15	1		T136	9		T141	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T137	13		T248	5		T329	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T168	10		T255	11		T337	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T68	7		T245	8		T206	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T67	10		T157	11		T139	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T261	14		T141	2		T153	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	390	1			T238	6		T139	14		T149	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T18	16		T21	7		T68	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

auto[0]

4255

1

T15

1

T18

16

T19

1