Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23324

1

T4

20

T5

14

T6

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19983

1

T4

20

T5

14

T6

2

auto[ADC_CTRL_FILTER_COND_OUT]

3341

1

T14

2

T17

12

T18

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17344

1

T4

20

T5

14

T6

2

auto[1]

5980

1

T15

2

T16

10

T19

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19611

1

T4

20

T5

14

T6

2

auto[1]

3713

1

T12

3

T14

2

T16

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	502	1			T237	21		T52	2		T64	1
values[0]	69	1			T160	1		T145	3		T42	27
values[1]	685	1			T6	2		T20	7		T84	19
values[2]	2960	1			T14	2		T23	15		T96	11
values[3]	640	1			T16	10		T19	2		T84	5
values[4]	538	1			T12	1		T137	11		T239	1
values[5]	545	1			T17	12		T22	23		T67	5
values[6]	579	1			T15	2		T136	16		T137	14
values[7]	596	1			T17	11		T20	3		T68	16
values[8]	598	1			T20	13		T67	25		T160	1
values[9]	1108	1			T18	27		T21	10		T68	25
minimum	14504	1			T4	20		T5	14		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	668	1			T14	2		T20	7		T84	19
values[1]	2908	1			T19	2		T23	15		T96	11
values[2]	617	1			T12	1		T16	10		T84	5
values[3]	590	1			T52	28		T239	1		T138	1
values[4]	531	1			T17	12		T22	23		T67	5
values[5]	639	1			T15	2		T20	3		T68	16
values[6]	550	1			T17	11		T168	21		T47	1
values[7]	570	1			T20	13		T67	25		T157	23
values[8]	1294	1			T18	27		T21	10		T68	25
values[9]	159	1			T139	25		T201	30		T274	11
minimum	14798	1			T4	20		T5	14		T6	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

4255

1

T15

1

T18

16

T19

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T20	1		T84	5		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	2		T156	1		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1668	1			T19	2		T23	15		T96	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T156	1		T247	11		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	1		T16	1		T54	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T84	3		T46	15		T240	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T138	1		T158	13		T286	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T52	13		T239	1		T196	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T22	12		T136	10		T42	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T17	1		T67	3		T244	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T15	2		T20	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T68	8		T137	14		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T17	1		T168	11		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T161	1		T245	9		T286	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T20	1		T67	11		T157	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T67	1		T246	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T62	2		T238	7		T64	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T18	17		T21	8		T68	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T139	15		T201	16		T274	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T176	1		T340	1		T381	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14496	1			T4	20		T5	14		T6	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T160	1		T42	12		T172	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T20	6		T84	14		T145	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T156	2		T150	14		T185	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	878	1			T159	10		T144	20		T55	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T156	14		T317	11		T274	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T16	9		T201	8		T242	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T84	2		T269	27		T165	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T158	13		T302	2		T292	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T52	15		T196	2		T260	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T22	11		T136	6		T42	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T17	11		T67	2		T244	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T20	2		T196	1		T244	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T68	8		T248	9		T371	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T17	10		T168	10		T270	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T206	15		T153	6		T372	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T20	12		T67	13		T157	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T261	10		T315	20		T152	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T238	4		T149	4		T250	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T18	10		T21	2		T68	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T139	10		T201	14		T374	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T340	13		T189	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	3		T14	2		T97	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T42	15		T267	8		T299	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T64	1		T139	15		T149	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T237	12		T52	1		T171	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T145	1		T173	7		T254	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T160	1		T42	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	2		T20	1		T84	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T148	1		T140	12		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1714	1			T23	15		T96	11		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	2		T156	1		T247	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T16	1		T19	2		T54	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T84	3		T156	1		T46	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	1		T137	11		T146	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T239	1		T196	13		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T22	12		T42	9		T158	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T17	1		T67	3		T52	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T15	2		T136	10		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T137	14		T138	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T17	1		T20	1		T168	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T68	8		T245	9		T286	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T20	1		T67	11		T157	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T67	1		T160	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T62	2		T238	7		T250	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T18	17		T21	8		T68	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14409	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T139	10		T149	4		T163	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T237	9		T52	1		T171	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T145	2		T173	7		T254	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T42	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T20	6		T84	14		T145	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T165	1		T290	13		T380	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	893	1			T159	10		T144	20		T55	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T156	2		T150	14		T185	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T16	9		T201	8		T242	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T84	2		T156	14		T269	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T260	6		T281	2		T302	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T196	2		T260	10		T257	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T22	11		T42	9		T158	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T17	11		T67	2		T52	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T136	6		T196	1		T244	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T248	9		T371	2		T287	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T17	10		T20	2		T168	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T68	8		T206	15		T208	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T20	12		T67	13		T157	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T261	10		T153	6		T372	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T238	4		T250	9		T212	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T18	10		T21	2		T68	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T20	7		T84	15		T145	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	2		T156	3		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T19	1		T23	1		T96	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T156	15		T247	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	1		T16	10		T54	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T84	3		T46	1		T240	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T138	1		T158	14		T286	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T52	16		T239	1		T196	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T22	12		T136	7		T42	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T17	12		T67	3		T244	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	1		T20	3		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T68	9		T137	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T17	11		T168	11		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T161	1		T245	1		T286	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T20	13		T67	14		T157	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T67	1		T246	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	399	1			T62	2		T238	5		T64	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T18	11		T21	3		T68	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T139	11		T201	15		T274	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T176	1		T340	14		T381	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14586	1			T4	20		T5	14		T6	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T160	1		T42	16		T172	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T84	4		T149	9		T185	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T140	11		T185	7		T165	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T19	1		T23	14		T96	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T247	10		T265	11		T317	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T54	8		T137	10		T201	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T84	2		T46	14		T269	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T158	12		T308	7		T302	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T52	12		T196	12		T260	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T22	11		T136	9		T42	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T67	2		T244	15		T151	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T15	1		T244	4		T248	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T68	7		T137	13		T248	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T168	10		T270	1		T322	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T245	8		T206	4		T288	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T67	10		T157	11		T139	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T261	14		T141	2		T315	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T238	6		T149	5		T250	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T18	16		T21	7		T68	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T139	14		T201	15		T274	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T381	5		T189	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T173	6		T277	16		T254	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T42	11		T172	16		T267	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T64	1		T139	11		T149	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T237	10		T52	2		T171	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T145	3		T173	8		T254	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T160	1		T42	16		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	2		T20	7		T84	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T148	1		T140	1		T165	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T23	1		T96	1		T159	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	2		T156	3		T247	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T16	10		T19	1		T54	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T84	3		T156	15		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T12	1		T137	1		T146	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T239	1		T196	3		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T22	12		T42	10		T158	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T17	12		T67	3		T52	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T15	1		T136	7		T196	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T137	1		T138	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T17	11		T20	3		T168	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T68	9		T245	1		T286	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T20	13		T67	14		T157	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T67	1		T160	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T62	2		T238	5		T250	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T18	11		T21	3		T68	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14504	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T139	14		T149	5		T163	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T237	11		T222	12		T331	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T173	6		T254	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T42	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T84	4		T149	9		T245	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T140	11		T290	13		T172	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T23	14		T96	10		T49	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T247	10		T185	7		T265	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T19	1		T54	8		T201	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T84	2		T46	14		T269	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T137	10		T260	6		T302	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T196	12		T260	7		T257	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T22	11		T42	8		T158	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T67	2		T52	12		T244	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T15	1		T136	9		T141	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T137	13		T248	5		T271	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T168	10		T248	2		T255	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T68	7		T245	8		T206	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T67	10		T157	11		T139	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T261	14		T141	2		T153	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T238	6		T250	8		T212	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T18	16		T21	7		T68	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

auto[0]

4255

1

T15

1

T18

16

T19

1