Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23324

1

T4

20

T5

14

T6

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17806

1

T4

20

T5

14

T6

2

auto[ADC_CTRL_FILTER_COND_OUT]

5518

1

T16

10

T17

12

T18

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17276

1

T4

20

T5

14

T7

20

auto[1]

6048

1

T6

2

T12

1

T14

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19611

1

T4

20

T5

14

T6

2

auto[1]

3713

1

T12

3

T14

2

T16

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	290	1			T67	24		T196	15		T185	36
values[0]	69	1			T382	29		T193	23		T291	17
values[1]	744	1			T12	1		T136	16		T156	3
values[2]	584	1			T14	2		T15	2		T160	1
values[3]	700	1			T20	7		T22	23		T160	1
values[4]	552	1			T17	11		T67	5		T68	16
values[5]	746	1			T18	27		T145	10		T146	2
values[6]	559	1			T17	12		T67	1		T168	21
values[7]	546	1			T20	13		T54	9		T47	1
values[8]	869	1			T19	2		T20	3		T156	15
values[9]	3161	1			T6	2		T16	10		T21	10
minimum	14504	1			T4	20		T5	14		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	731	1			T12	1		T14	2		T136	16
values[1]	2806	1			T15	2		T20	7		T23	15
values[2]	658	1			T22	23		T160	1		T145	3
values[3]	638	1			T17	11		T67	5		T68	16
values[4]	704	1			T18	27		T237	21		T145	10
values[5]	550	1			T17	12		T20	13		T67	1
values[6]	659	1			T54	9		T161	1		T157	23
values[7]	751	1			T19	2		T20	3		T68	25
values[8]	950	1			T6	2		T16	10		T21	10
values[9]	118	1			T196	15		T248	10		T265	9
minimum	14759	1			T4	20		T5	14		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

4255

1

T15

1

T18

16

T19

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	1		T14	2		T136	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T156	1		T138	1		T196	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T15	2		T84	3		T46	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1625	1			T20	1		T23	15		T96	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T52	13		T148	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T22	12		T160	1		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T17	1		T67	3		T68	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T148	1		T244	16		T142	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T146	2		T139	15		T140	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T18	17		T237	12		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T20	1		T67	1		T168	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T17	1		T47	1		T241	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T54	9		T161	1		T185	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T157	12		T150	1		T270	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T20	1		T156	1		T238	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T19	2		T68	11		T249	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T6	2		T67	11		T236	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T16	1		T21	8		T62	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T248	6		T206	11		T302	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T196	13		T265	9		T255	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14509	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T42	9		T280	1		T164	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T136	6		T201	14		T202	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T156	2		T196	1		T149	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T84	2		T311	1		T269	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	855	1			T20	6		T159	10		T144	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T52	15		T150	14		T260	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T22	11		T145	2		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T17	10		T67	2		T68	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T244	14		T266	11		T302	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T139	10		T149	10		T165	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T18	10		T237	9		T145	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T20	12		T168	10		T196	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T17	11		T241	7		T316	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T185	7		T202	6		T269	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T157	11		T270	1		T282	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T20	2		T156	14		T238	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T68	14		T257	17		T248	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T67	13		T242	3		T290	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T16	9		T21	2		T42	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T248	4		T206	5		T302	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T196	2		T255	3		T341	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	3		T14	2		T97	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T42	9		T164	11		T110	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T67	11		T236	1		T290	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T196	13		T185	19		T265	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T193	17		T291	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T382	20		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	1		T136	10		T261	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T156	1		T42	9		T196	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	2		T15	2		T84	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T160	1		T138	1		T140	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T52	13		T148	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T20	1		T22	12		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T17	1		T67	3		T68	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T52	1		T212	13		T244	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T146	2		T139	15		T140	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T18	17		T145	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T67	1		T168	11		T247	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T17	1		T237	12		T241	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T20	1		T54	9		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T47	1		T157	12		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T20	1		T156	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T19	2		T257	14		T248	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	2		T238	7		T140	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1772	1			T16	1		T21	8		T23	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14409	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T67	13		T290	13		T302	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T196	2		T185	17		T166	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T193	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T382	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T136	6		T261	10		T201	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T156	2		T42	9		T196	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T84	2		T311	1		T242	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T248	9		T315	20		T166	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T52	15		T150	14		T260	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T20	6		T22	11		T145	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T17	10		T67	2		T68	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T52	1		T212	9		T244	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T139	10		T149	10		T171	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T18	10		T145	9		T139	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T168	10		T243	2		T165	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T17	11		T237	9		T241	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T20	12		T196	1		T260	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T157	11		T270	1		T282	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T20	2		T156	14		T250	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T257	17		T248	11		T269	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T238	4		T248	4		T242	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	993	1			T16	9		T21	2		T68	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	1		T14	2		T136	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T156	3		T138	1		T196	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T15	1		T84	3		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1180	1			T20	7		T23	1		T96	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T52	16		T148	1		T150	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T22	12		T160	1		T145	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T17	11		T67	3		T68	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T148	1		T244	15		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T146	2		T139	11		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T18	11		T237	10		T145	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T20	13		T67	1		T168	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T17	12		T47	1		T241	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T54	1		T161	1		T185	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T157	12		T150	1		T270	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T20	3		T156	15		T238	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T19	1		T68	15		T249	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T6	2		T67	14		T236	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T16	10		T21	3		T62	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T248	5		T206	6		T302	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T196	3		T265	1		T255	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14559	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T42	10		T280	1		T164	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T136	9		T201	15		T153	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T149	5		T248	5		T172	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T84	2		T46	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1300	1			T23	14		T96	10		T49	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T52	12		T260	6		T163	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T22	11		T212	12		T319	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T67	2		T68	7		T84	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T244	15		T142	16		T308	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T139	14		T140	11		T149	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T18	16		T237	11		T139	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T168	10		T247	10		T260	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T245	15		T316	7		T306	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T54	8		T185	7		T269	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T157	11		T270	1		T151	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T238	6		T140	6		T250	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T19	1		T68	10		T257	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T67	10		T290	21		T322	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T21	7		T42	11		T137	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T248	5		T206	10		T302	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T196	12		T265	8		T102	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T261	14		T172	16		T267	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T42	8		T164	9		T110	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T67	14		T236	1		T290	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T196	3		T185	18		T265	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T193	7		T291	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T382	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	1		T136	7		T261	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T156	3		T42	10		T196	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T14	2		T15	1		T84	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T160	1		T138	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T52	16		T148	1		T150	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T20	7		T22	12		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T17	11		T67	3		T68	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T52	2		T212	10		T244	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T146	2		T139	11		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T18	11		T145	10		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T67	1		T168	11		T247	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T17	12		T237	10		T241	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T20	13		T54	1		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T47	1		T157	12		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T20	3		T156	15		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T19	1		T257	19		T248	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T6	2		T238	5		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1339	1			T16	10		T21	3		T23	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14504	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T67	10		T290	13		T302	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T196	12		T185	18		T265	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T193	16		T291	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T382	19		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T136	9		T261	14		T201	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T42	8		T149	5		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	1		T84	2		T46	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T140	13		T248	5		T315	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T52	12		T260	6		T163	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T22	11		T319	17		T259	29
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T67	2		T68	7		T84	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T212	12		T244	15		T308	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T139	14		T140	11		T149	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T18	16		T139	2		T142	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T168	10		T247	10		T245	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T237	11		T245	8		T316	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T54	8		T260	7		T320	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T157	11		T270	1		T245	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T250	8		T185	7		T141	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T19	1		T257	12		T248	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T238	6		T140	6		T248	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1426	1			T21	7		T23	14		T68	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

auto[0]

4255

1

T15

1

T18

16

T19

1