Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T12	1		T60	1		T14	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T285	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T278	1		T210	13		T189	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T177	1		T188	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T14	2		T15	2		T17	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T249	1		T146	2		T279	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1632	1			T18	17		T23	15		T96	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T270	4		T201	7		T163	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	1		T22	12		T62	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T145	1		T52	1		T140	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T260	7		T269	11		T286	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T68	11		T160	1		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T16	1		T67	11		T84	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T197	1		T150	1		T202	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T67	3		T54	9		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T67	1		T52	13		T42	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T145	1		T138	1		T142	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T20	1		T68	8		T237	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T21	8		T148	1		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T17	1		T46	15		T137	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	419	1			T6	2		T84	3		T136	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T19	2		T20	2		T160	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14101	1			T4	20		T5	14		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T210	11		T189	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T188	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T17	10		T168	10		T42	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T255	13		T166	19		T287	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	855	1			T18	10		T159	10		T144	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T270	1		T201	8		T163	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T22	11		T158	13		T222	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T145	9		T52	1		T171	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T260	6		T269	11		T242	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T68	14		T164	11		T268	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T16	9		T67	13		T84	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T202	10		T151	11		T153	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T67	2		T157	11		T196	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T52	15		T42	15		T261	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T145	2		T257	7		T282	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T20	6		T68	8		T237	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T21	2		T283	1		T273	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	11		T149	14		T248	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T84	2		T136	6		T257	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T20	14		T156	16		T139	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	2		T15	1		T17	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T249	1		T146	2		T279	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T12	1		T18	11		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T140	1		T244	15		T270	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T22	12		T162	1		T269	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T160	1		T145	10		T52	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T84	15		T150	15		T260	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T68	15		T148	1		T197	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T16	10		T67	14		T247	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T42	16		T150	1		T185	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T67	3		T145	3		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T67	1		T68	9		T52	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T47	1		T142	1		T280	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T20	7		T237	10		T46	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T137	1		T148	1		T240	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T17	12		T137	1		T149	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T21	3		T236	1		T248	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T19	1		T20	16		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T6	2		T84	3		T136	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T64	1		T196	2		T250	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14504	1			T4	20		T5	14		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T15	1		T168	10		T165	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T245	13		T255	11		T288	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T18	16		T23	14		T96	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T140	13		T244	15		T270	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T22	11		T162	12		T269	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T140	11		T212	12		T141	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T84	4		T260	6		T222	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T68	10		T268	9		T153	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T67	10		T247	10		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T42	11		T185	7		T151	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T67	2		T54	8		T260	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T68	7		T52	12		T261	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T142	2		T284	21		T289	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T237	11		T46	14		T238	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T137	10		T277	5		T35	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T137	13		T149	9		T248	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T21	7		T248	5		T245	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T19	1		T139	14		T290	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T84	2		T136	9		T257	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T250	8		T244	4		T265	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T12	1		T60	1		T14	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T285	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T278	1		T210	12		T189	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T177	1		T188	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T14	2		T15	1		T17	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T249	1		T146	2		T279	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1192	1			T18	11		T23	1		T96	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T270	4		T201	9		T163	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	1		T22	12		T62	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T145	10		T52	2		T140	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T260	7		T269	12		T286	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T68	15		T160	1		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	10		T67	14		T84	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T197	1		T150	1		T202	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T67	3		T54	1		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T67	1		T52	16		T42	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T145	3		T138	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T20	7		T68	9		T237	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T21	3		T148	1		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T17	12		T46	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	383	1			T6	2		T84	3		T136	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T19	1		T20	16		T160	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14196	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T285	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T210	12		T189	7		T291	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T188	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T15	1		T168	10		T42	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T245	13		T255	11		T166	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T18	16		T23	14		T96	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T270	1		T201	6		T163	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T22	11		T158	12		T162	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T140	24		T212	12		T141	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T260	6		T269	10		T206	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T68	10		T164	9		T268	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T67	10		T84	4		T247	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T151	11		T153	10		T292	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T67	2		T54	8		T157	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T52	12		T42	11		T261	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T142	2		T257	3		T277	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T68	7		T237	11		T238	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T21	7		T35	1		T273	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T46	14		T137	13		T149	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T84	2		T136	9		T137	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T19	1		T139	14		T250	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

auto[0]

4255

1

T15

1

T18

16

T19

1