Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23324

1

T4

20

T5

14

T6

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20052

1

T4

20

T5

14

T7

20

auto[ADC_CTRL_FILTER_COND_OUT]

3272

1

T6

2

T12

1

T15

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17480

1

T4

20

T5

14

T6

2

auto[1]

5844

1

T14

2

T17

23

T18

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19611

1

T4

20

T5

14

T6

2

auto[1]

3713

1

T12

3

T14

2

T16

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T293	1		-	-		-	-
values[0]	58	1			T54	9		T294	1		T295	12
values[1]	561	1			T145	3		T42	27		T46	15
values[2]	674	1			T15	2		T19	2		T20	7
values[3]	813	1			T160	1		T84	19		T52	28
values[4]	583	1			T12	1		T16	10		T20	13
values[5]	2961	1			T20	3		T23	15		T96	11
values[6]	831	1			T14	2		T17	23		T18	27
values[7]	676	1			T6	2		T67	24		T68	16
values[8]	547	1			T67	1		T68	25		T84	5
values[9]	1115	1			T21	10		T22	23		T67	5
minimum	14504	1			T4	20		T5	14		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	792	1			T145	3		T54	9		T42	27
values[1]	754	1			T15	2		T19	2		T20	7
values[2]	794	1			T12	1		T16	10		T52	30
values[3]	2728	1			T20	13		T23	15		T96	11
values[4]	765	1			T18	27		T20	3		T168	21
values[5]	918	1			T6	2		T14	2		T17	11
values[6]	545	1			T17	12		T148	1		T139	25
values[7]	579	1			T67	1		T68	25		T84	5
values[8]	806	1			T21	10		T62	2		T160	1
values[9]	134	1			T22	23		T67	5		T47	1
minimum	14509	1			T4	20		T5	14		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

4255

1

T15

1

T18

16

T19

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T46	15		T148	1		T197	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T145	1		T54	9		T42	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T19	2		T84	5		T261	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T15	2		T20	1		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T16	1		T52	1		T146	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	1		T52	13		T138	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1698	1			T20	1		T23	15		T96	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T137	14		T279	1		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T18	17		T20	1		T42	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T168	11		T237	12		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T14	2		T67	11		T247	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T6	2		T17	1		T68	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T148	1		T149	6		T244	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T17	1		T139	15		T140	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T67	1		T84	3		T244	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T68	11		T137	11		T64	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T21	8		T62	2		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T156	1		T250	9		T142	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T67	3		T296	1		T297	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T22	12		T47	1		T185	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14409	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T298	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T270	1		T248	4		T281	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T145	2		T42	15		T243	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T84	14		T261	10		T260	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T20	6		T139	5		T158	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T16	9		T52	1		T196	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T52	15		T185	17		T260	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	852	1			T20	12		T159	10		T144	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T299	6		T300	11		T301	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T18	10		T20	2		T42	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T168	10		T237	9		T145	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T67	13		T157	11		T150	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T17	10		T68	8		T136	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T149	4		T244	14		T257	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T17	11		T139	10		T302	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T84	2		T244	2		T201	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T68	14		T196	1		T266	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T21	2		T255	3		T268	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T156	2		T250	9		T222	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T67	2		T303	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T22	11		T185	7		T259	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T298	4		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T293	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T295	1		T304	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T54	9		T294	1		T305	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T46	15		T148	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T145	1		T42	12		T243	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T19	2		T197	1		T261	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T15	2		T20	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T84	5		T196	13		T260	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T160	1		T52	13		T137	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T16	1		T20	1		T52	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	1		T138	1		T260	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1759	1			T20	1		T23	15		T96	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T168	11		T145	1		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	2		T18	17		T42	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T17	2		T136	10		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T67	11		T247	11		T157	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	2		T68	8		T139	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T67	1		T84	3		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T68	11		T64	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T21	8		T67	3		T62	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T22	12		T156	1		T47	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14409	1			T4	20		T5	14		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T295	11		T304	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T305	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T248	4		T281	2		T282	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T145	2		T42	15		T243	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T261	10		T270	1		T165	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T20	6		T149	10		T262	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T84	14		T196	2		T260	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T52	15		T139	5		T185	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T16	9		T20	12		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T260	6		T269	11		T290	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	893	1			T20	2		T159	10		T144	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T168	10		T145	9		T196	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T18	10		T42	9		T150	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T17	21		T136	6		T156	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T67	13		T157	11		T149	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T68	8		T139	10		T155	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T84	2		T244	2		T173	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T68	14		T266	11		T165	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T21	2		T67	2		T201	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T22	11		T156	2		T196	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T46	1		T148	1		T197	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T145	3		T54	1		T42	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T19	1		T84	15		T261	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T15	1		T20	7		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T16	10		T52	2		T146	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T12	1		T52	16		T138	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1182	1			T20	13		T23	1		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T137	1		T279	1		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T18	11		T20	3		T42	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T168	11		T237	10		T145	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T14	2		T67	14		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T6	2		T17	11		T68	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T148	1		T149	5		T244	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T17	12		T139	11		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T67	1		T84	3		T244	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T68	15		T137	1		T64	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T21	3		T62	2		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T156	3		T250	10		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T67	3		T296	1		T297	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T22	12		T47	1		T185	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14504	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T298	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T46	14		T270	1		T248	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T54	8		T42	11		T140	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T19	1		T84	4		T261	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T15	1		T139	2		T158	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T196	12		T245	15		T172	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T52	12		T185	18		T260	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T23	14		T96	10		T49	32
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T137	13		T265	8		T306	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T18	16		T42	8		T238	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T168	10		T237	11		T248	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T67	10		T247	10		T157	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T68	7		T136	9		T162	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T149	5		T244	15		T142	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T139	14		T140	6		T141	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T84	2		T244	4		T201	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T68	10		T137	10		T162	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T21	7		T140	13		T268	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T250	8		T142	16		T245	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T67	2		T303	1		T307	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T22	11		T185	7		T259	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T293	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T295	12		T304	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T54	1		T294	1		T305	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T46	1		T148	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T145	3		T42	16		T243	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T19	1		T197	1		T261	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T15	1		T20	7		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T84	15		T196	3		T260	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T160	1		T52	16		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T16	10		T20	13		T52	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	1		T138	1		T260	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1223	1			T20	3		T23	1		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T168	11		T145	10		T196	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	2		T18	11		T42	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T17	23		T136	7		T156	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T67	14		T247	1		T157	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T6	2		T68	9		T139	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T67	1		T84	3		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T68	15		T64	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T21	3		T67	3		T62	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T22	12		T156	3		T47	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14504	1			T4	20		T5	14		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T304	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T54	8		T305	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T46	14		T248	5		T166	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T42	11		T201	15		T259	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T19	1		T261	14		T270	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T15	1		T140	11		T149	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T84	4		T196	12		T260	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T52	12		T137	13		T139	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T141	15		T172	11		T151	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T260	6		T265	8		T269	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1429	1			T23	14		T96	10		T49	32
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T168	10		T308	7		T271	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T18	16		T42	8		T212	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T136	9		T237	11		T162	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T67	10		T247	10		T157	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T68	7		T139	14		T141	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T84	2		T244	4		T173	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T68	10		T140	6		T162	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T21	7		T67	2		T140	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T22	11		T137	10		T250	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

auto[0]

4255

1

T15

1

T18

16

T19

1