Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23324

1

T4

20

T5

14

T6

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17760

1

T4

20

T5

14

T6

2

auto[ADC_CTRL_FILTER_COND_OUT]

5564

1

T16

10

T17

12

T18

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17255

1

T4

20

T5

14

T7

20

auto[1]

6069

1

T6

2

T12

1

T14

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19611

1

T4

20

T5

14

T6

2

auto[1]

3713

1

T12

3

T14

2

T16

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	49	1			T110	6		T309	15		T300	13
values[0]	64	1			T12	1		T310	11		T193	23
values[1]	759	1			T136	16		T42	18		T138	1
values[2]	579	1			T14	2		T15	2		T160	1
values[3]	684	1			T20	7		T22	23		T160	1
values[4]	602	1			T17	11		T67	5		T68	16
values[5]	687	1			T18	27		T168	21		T145	10
values[6]	543	1			T67	1		T237	21		T139	25
values[7]	582	1			T17	12		T20	13		T54	9
values[8]	828	1			T19	2		T20	3		T156	15
values[9]	3443	1			T6	2		T16	10		T21	10
minimum	14504	1			T4	20		T5	14		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	983	1			T12	1		T14	2		T136	16
values[1]	2764	1			T20	7		T23	15		T96	11
values[2]	694	1			T15	2		T17	11		T22	23
values[3]	652	1			T67	5		T68	16		T84	19
values[4]	699	1			T18	27		T67	1		T237	21
values[5]	568	1			T17	12		T20	13		T168	21
values[6]	613	1			T54	9		T161	1		T157	23
values[7]	756	1			T19	2		T20	3		T68	25
values[8]	884	1			T6	2		T16	10		T21	10
values[9]	207	1			T62	2		T137	11		T196	15
minimum	14504	1			T4	20		T5	14		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

4255

1

T15

1

T18

16

T19

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T12	1		T14	2		T136	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T156	1		T42	9		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T46	15		T138	1		T236	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1625	1			T20	1		T23	15		T96	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	2		T17	1		T84	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T22	12		T160	1		T246	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T67	3		T68	8		T84	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T52	1		T239	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T67	1		T146	2		T139	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T18	17		T237	12		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T20	1		T247	11		T196	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T17	1		T168	11		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T54	9		T161	1		T202	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T157	12		T150	1		T141	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T20	1		T156	1		T238	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T19	2		T68	11		T249	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T6	2		T67	11		T236	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T16	1		T21	8		T42	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T248	6		T51	1		T302	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T62	2		T137	11		T196	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14409	1			T4	20		T5	14		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T136	6		T261	10		T201	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T156	2		T42	9		T196	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T311	1		T269	1		T242	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	851	1			T20	6		T159	10		T144	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T17	10		T84	2		T145	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T22	11		T212	9		T312	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T67	2		T68	8		T84	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T52	1		T244	14		T266	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T139	10		T149	10		T165	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T18	10		T237	9		T145	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T20	12		T196	1		T243	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T17	11		T168	10		T241	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T202	6		T269	11		T268	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T157	11		T270	1		T282	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T20	2		T156	14		T238	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T68	14		T257	17		T248	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T67	13		T201	18		T242	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T16	9		T21	2		T42	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T248	4		T302	11		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T196	2		T244	2		T255	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T309	8		T300	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T110	5		T313	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T12	1		T310	6		T193	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T314	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T136	10		T138	1		T261	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T42	9		T196	1		T149	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	2		T15	2		T84	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T160	1		T156	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T145	1		T52	13		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T20	1		T22	12		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T17	1		T67	3		T68	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T52	1		T239	1		T212	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T247	11		T146	2		T140	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T18	17		T168	11		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T67	1		T139	15		T197	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T237	12		T245	9		T268	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T20	1		T54	9		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T17	1		T47	1		T157	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T20	1		T156	1		T140	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T19	2		T141	3		T257	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T6	2		T67	11		T238	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1853	1			T16	1		T21	8		T23	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14409	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T309	7		T300	12		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T110	1		T313	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T310	5		T193	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T136	6		T261	10		T201	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T42	9		T196	1		T149	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T84	2		T242	8		T277	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T156	2		T248	9		T315	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T145	2		T52	15		T150	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T20	6		T22	11		T262	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T17	10		T67	2		T68	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T52	1		T212	9		T244	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T149	10		T171	1		T201	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T18	10		T168	10		T145	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T139	10		T243	2		T165	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T237	9		T316	11		T284	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T20	12		T196	1		T260	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T17	11		T157	11		T270	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T20	2		T156	14		T250	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T257	17		T248	11		T269	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T67	13		T238	4		T248	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1081	1			T16	9		T21	2		T68	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T12	1		T14	2		T136	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T156	3		T42	10		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T46	1		T138	1		T236	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1176	1			T20	7		T23	1		T96	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T15	1		T17	11		T84	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T22	12		T160	1		T246	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T67	3		T68	9		T84	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T52	2		T239	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T67	1		T146	2		T139	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T18	11		T237	10		T145	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T20	13		T247	1		T196	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T17	12		T168	11		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T54	1		T161	1		T202	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T157	12		T150	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T20	3		T156	15		T238	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T19	1		T68	15		T249	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T6	2		T67	14		T236	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T16	10		T21	3		T42	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T248	5		T51	1		T302	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T62	2		T137	1		T196	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14504	1			T4	20		T5	14		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T136	9		T261	14		T201	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T42	8		T149	5		T248	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T46	14		T311	1		T317	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1300	1			T23	14		T96	10		T49	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T15	1		T84	2		T52	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T22	11		T212	12		T302	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T67	2		T68	7		T84	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T244	15		T142	16		T308	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T139	14		T140	11		T149	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T18	16		T237	11		T139	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T247	10		T260	7		T245	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T168	10		T245	15		T316	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T54	8		T269	10		T268	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T157	11		T141	2		T270	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T238	6		T140	6		T250	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T19	1		T68	10		T257	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T67	10		T201	20		T290	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T21	7		T42	11		T137	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T248	5		T302	17		T313	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T137	10		T196	12		T244	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T309	8		T300	13		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T110	2		T313	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T12	1		T310	6		T193	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T314	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T136	7		T138	1		T261	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T42	10		T196	2		T149	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T14	2		T15	1		T84	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T160	1		T156	3		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T145	3		T52	16		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T20	7		T22	12		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T17	11		T67	3		T68	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T52	2		T239	1		T212	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T247	1		T146	2		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T18	11		T168	11		T145	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T67	1		T139	11		T197	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T237	10		T245	1		T268	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T20	13		T54	1		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T17	12		T47	1		T157	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T20	3		T156	15		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T19	1		T141	1		T257	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T6	2		T67	14		T238	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1440	1			T16	10		T21	3		T23	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14504	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T309	7		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T110	4		T313	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T310	5		T193	16		T318	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T136	9		T261	14		T201	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T42	8		T149	5		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T84	2		T46	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T140	13		T248	5		T315	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T52	12		T260	6		T163	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T22	11		T319	17		T259	29
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T67	2		T68	7		T84	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T212	12		T244	15		T142	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T247	10		T140	11		T149	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T18	16		T168	10		T139	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T139	14		T245	13		T165	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T237	11		T245	8		T316	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T54	8		T260	7		T320	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T157	11		T270	1		T245	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T140	6		T250	8		T185	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T19	1		T141	2		T257	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T67	10		T238	6		T248	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1494	1			T21	7		T23	14		T68	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

auto[0]

4255

1

T15

1

T18

16

T19

1