Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23324

1

T4

20

T5

14

T6

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20194

1

T4

20

T5

14

T6

2

auto[ADC_CTRL_FILTER_COND_OUT]

3130

1

T14

2

T15

2

T17

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17307

1

T4

20

T5

14

T7

20

auto[1]

6017

1

T6

2

T15

2

T17

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19611

1

T4

20

T5

14

T6

2

auto[1]

3713

1

T12

3

T14

2

T16

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	24	1			T259	5		T321	2		T291	17
values[0]	52	1			T279	1		T173	21		T319	20
values[1]	613	1			T67	5		T156	3		T54	9
values[2]	694	1			T64	1		T138	1		T148	1
values[3]	613	1			T20	13		T138	1		T150	1
values[4]	2836	1			T15	2		T19	2		T23	15
values[5]	654	1			T68	16		T160	1		T84	19
values[6]	710	1			T21	10		T67	1		T68	25
values[7]	626	1			T6	2		T14	2		T17	11
values[8]	792	1			T52	2		T238	11		T247	11
values[9]	1206	1			T12	1		T16	10		T17	12
minimum	14504	1			T4	20		T5	14		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	708	1			T67	5		T156	3		T42	45
values[1]	855	1			T54	9		T64	1		T138	2
values[2]	505	1			T15	2		T20	13		T185	51
values[3]	2893	1			T19	2		T23	15		T96	11
values[4]	727	1			T67	1		T68	41		T84	19
values[5]	543	1			T6	2		T21	10		T168	21
values[6]	531	1			T14	2		T17	11		T20	10
values[7]	1017	1			T17	12		T67	24		T136	16
values[8]	727	1			T12	1		T16	10		T160	1
values[9]	292	1			T18	27		T84	5		T47	1
minimum	14526	1			T4	20		T5	14		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

4255

1

T15

1

T18

16

T19

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T67	3		T156	1		T42	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T42	9		T157	12		T196	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T54	9		T64	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T138	1		T196	13		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T20	1		T185	27		T260	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T15	2		T162	13		T201	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1688	1			T19	2		T23	15		T96	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T160	1		T145	1		T141	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T67	1		T161	1		T257	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T68	19		T84	5		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	2		T168	11		T52	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T21	8		T139	3		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T243	1		T236	1		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	2		T17	1		T20	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T237	12		T52	1		T249	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T17	1		T67	11		T136	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T12	1		T16	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T139	15		T236	1		T201	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T18	17		T84	3		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T240	1		T265	12		T322	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14431	1			T4	20		T5	14		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T67	2		T156	2		T42	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T42	9		T157	11		T196	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T212	9		T269	16		T222	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T196	2		T312	6		T151	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T20	12		T185	24		T260	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T201	8		T277	6		T323	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	916	1			T159	10		T144	20		T55	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T145	9		T244	2		T242	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T257	7		T165	1		T152	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T68	22		T84	14		T257	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T168	10		T52	15		T260	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T21	2		T139	5		T196	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T243	2		T290	13		T206	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T17	10		T20	8		T22	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T237	9		T52	1		T244	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T17	11		T67	13		T136	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T16	9		T238	4		T150	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T139	10		T201	18		T255	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T18	10		T84	2		T158	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T324	7		T263	7		T325	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T259	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T321	1		T291	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T173	12		T319	15		T326	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T279	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T67	3		T156	1		T54	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T42	9		T157	12		T196	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T64	1		T148	1		T212	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T138	1		T196	13		T280	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T20	1		T138	1		T185	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T150	1		T162	13		T201	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1678	1			T19	2		T23	15		T96	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T15	2		T242	1		T290	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T161	1		T150	1		T171	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T68	8		T160	1		T84	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T67	1		T52	13		T137	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T21	8		T68	11		T139	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	2		T168	11		T243	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	2		T17	1		T20	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T52	1		T238	7		T140	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T247	11		T246	1		T236	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T12	1		T16	1		T18	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T17	1		T67	11		T136	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14409	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T259	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T321	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T173	9		T319	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T67	2		T156	2		T42	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T42	9		T157	11		T196	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T212	9		T269	16		T165	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T196	2		T255	3		T151	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T20	12		T185	7		T260	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T201	8		T312	6		T277	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	926	1			T159	10		T144	20		T55	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T242	3		T290	12		T206	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T171	1		T257	7		T152	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T68	8		T84	14		T145	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T52	15		T260	10		T283	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T21	2		T68	14		T139	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T168	10		T243	2		T290	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T17	10		T20	8		T22	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T52	1		T238	4		T244	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T202	6		T311	1		T165	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T16	9		T18	10		T84	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T17	11		T67	13		T136	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T67	3		T156	3		T42	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T42	10		T157	12		T196	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T54	1		T64	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T138	1		T196	3		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T20	13		T185	26		T260	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T15	1		T162	1		T201	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T19	1		T23	1		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T160	1		T145	10		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T67	1		T161	1		T257	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T68	24		T84	15		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T6	2		T168	11		T52	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T21	3		T139	6		T196	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T243	3		T236	1		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T14	2		T17	11		T20	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T237	10		T52	2		T249	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T17	12		T67	14		T136	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T12	1		T16	10		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T139	11		T236	1		T201	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T18	11		T84	3		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T240	1		T265	1		T322	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14506	1			T4	20		T5	14		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T67	2		T42	11		T142	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T42	8		T157	11		T149	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T54	8		T212	12		T269	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T196	12		T151	11		T327	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T185	25		T260	6		T172	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	1		T162	12		T201	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T19	1		T23	14		T96	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T141	15		T244	4		T290	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T257	3		T172	16		T328	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T68	17		T84	4		T257	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T168	10		T52	12		T137	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T21	7		T139	2		T250	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T290	13		T206	10		T329	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T22	11		T247	10		T261	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T237	11		T140	17		T141	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T67	10		T136	9		T137	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T46	14		T238	6		T140	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T139	14		T201	20		T255	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T18	16		T84	2		T158	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T265	11		T322	8		T324	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T285	6		T330	14		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T259	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T321	2		T291	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T173	10		T319	6		T326	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T279	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T67	3		T156	3		T54	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T42	10		T157	12		T196	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T64	1		T148	1		T212	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T138	1		T196	3		T280	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T20	13		T138	1		T185	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T150	1		T162	1		T201	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T19	1		T23	1		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T15	1		T242	4		T290	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T161	1		T150	1		T171	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T68	9		T160	1		T84	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T67	1		T52	16		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T21	3		T68	15		T139	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	2		T168	11		T243	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	2		T17	11		T20	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T52	2		T238	5		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T247	1		T246	1		T236	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T12	1		T16	10		T18	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T17	12		T67	14		T136	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14504	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T259	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T291	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T173	11		T319	14		T326	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T67	2		T54	8		T42	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T42	8		T157	11		T149	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T212	12		T269	14		T165	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T196	12		T151	11		T327	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T185	7		T260	6		T172	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T162	12		T201	6		T245	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T19	1		T23	14		T96	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T15	1		T290	8		T206	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T257	3		T316	14		T306	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T68	7		T84	4		T141	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T52	12		T137	13		T260	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T21	7		T68	10		T139	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T168	10		T140	6		T290	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T22	11		T261	14		T271	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T238	6		T140	11		T244	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T247	10		T311	1		T151	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T18	16		T84	2		T237	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T67	10		T136	9		T137	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

auto[0]

4255

1

T15

1

T18

16

T19

1