Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23324

1

T4

20

T5

14

T6

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20070

1

T4

20

T5

14

T6

2

auto[ADC_CTRL_FILTER_COND_OUT]

3254

1

T12

1

T15

2

T17

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17560

1

T4

20

T5

14

T6

2

auto[1]

5764

1

T17

23

T18

27

T20

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19611

1

T4

20

T5

14

T6

2

auto[1]

3713

1

T12

3

T14

2

T16

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	249	1			T62	2		T156	3		T47	1
values[0]	9	1			T54	9		-	-		-	-
values[1]	631	1			T145	3		T42	27		T46	15
values[2]	627	1			T15	2		T19	2		T20	7
values[3]	838	1			T16	10		T84	19		T52	28
values[4]	631	1			T12	1		T20	13		T52	2
values[5]	2947	1			T18	27		T20	3		T23	15
values[6]	760	1			T14	2		T17	11		T136	16
values[7]	697	1			T6	2		T17	12		T67	24
values[8]	586	1			T67	1		T68	25		T84	5
values[9]	845	1			T21	10		T22	23		T67	5
minimum	14504	1			T4	20		T5	14		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	526	1			T145	3		T42	27		T46	15
values[1]	711	1			T15	2		T19	2		T20	7
values[2]	862	1			T12	1		T16	10		T52	30
values[3]	2759	1			T20	13		T23	15		T96	11
values[4]	764	1			T18	27		T20	3		T168	21
values[5]	909	1			T6	2		T14	2		T17	11
values[6]	477	1			T17	12		T148	1		T139	25
values[7]	538	1			T67	1		T68	25		T84	5
values[8]	967	1			T21	10		T67	5		T62	2
values[9]	41	1			T22	23		T47	1		T296	1
minimum	14770	1			T4	20		T5	14		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

4255

1

T15

1

T18

16

T19

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T46	15		T197	1		T270	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T145	1		T42	12		T140	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T19	2		T84	5		T201	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T15	2		T20	1		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T16	1		T146	2		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	1		T52	14		T137	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1691	1			T20	1		T23	15		T96	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T279	1		T163	1		T265	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T18	17		T20	1		T42	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T168	11		T237	12		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T6	2		T14	2		T67	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T17	1		T68	8		T136	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T148	1		T149	6		T244	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T17	1		T139	15		T140	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T67	1		T84	3		T244	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T68	11		T137	11		T64	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T21	8		T67	3		T62	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T156	1		T196	1		T250	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T296	1		T303	2		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T22	12		T47	1		T293	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14493	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T54	9		T243	1		T201	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T270	1		T281	2		T282	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T145	2		T42	15		T149	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T84	14		T201	8		T202	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T20	6		T139	5		T261	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T16	9		T196	2		T202	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T52	16		T185	17		T260	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	857	1			T20	12		T159	10		T144	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T269	11		T153	6		T190	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T18	10		T20	2		T42	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T168	10		T237	9		T145	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T67	13		T157	11		T150	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T17	10		T68	8		T136	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T149	4		T244	14		T173	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T17	11		T139	10		T331	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T84	2		T244	2		T206	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T68	14		T266	11		T242	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T21	2		T67	2		T201	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T156	2		T196	1		T250	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T303	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T22	11		T332	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	3		T14	2		T97	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T243	2		T201	14		T333	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T62	2		T296	1		T293	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T156	1		T47	1		T185	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T54	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T46	15		T148	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T145	1		T42	12		T243	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T19	2		T197	1		T270	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T15	2		T20	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T16	1		T84	5		T196	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T52	13		T137	14		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T20	1		T249	1		T146	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	1		T52	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1757	1			T18	17		T20	1		T23	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T168	11		T145	1		T265	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T14	2		T42	9		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T17	1		T136	10		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T6	2		T67	11		T247	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T17	1		T68	8		T139	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T67	1		T84	3		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T68	11		T64	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T21	8		T67	3		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T22	12		T137	11		T196	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14409	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T334	8		T335	23		T187	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T156	2		T185	7		T277	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T248	4		T281	2		T282	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T145	2		T42	15		T243	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T270	1		T165	1		T255	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T20	6		T261	10		T262	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T16	9		T84	14		T196	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T52	15		T139	5		T185	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T20	12		T151	6		T273	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T52	1		T260	6		T269	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	899	1			T18	10		T20	2		T159	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T168	10		T145	9		T153	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T42	9		T150	14		T171	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T17	10		T136	6		T156	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T67	13		T157	11		T149	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T17	11		T68	8		T139	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T84	2		T244	16		T173	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T68	14		T266	11		T165	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T21	2		T67	2		T201	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T22	11		T196	1		T250	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T46	1		T197	1		T270	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T145	3		T42	16		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T19	1		T84	15		T201	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T15	1		T20	7		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T16	10		T146	2		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T12	1		T52	18		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T20	13		T23	1		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T279	1		T163	1		T265	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T18	11		T20	3		T42	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T168	11		T237	10		T145	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T6	2		T14	2		T67	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T17	11		T68	9		T136	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T148	1		T149	5		T244	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T17	12		T139	11		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T67	1		T84	3		T244	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T68	15		T137	1		T64	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T21	3		T67	3		T62	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T156	3		T196	2		T250	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T296	1		T303	3		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T22	12		T47	1		T293	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14584	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T54	1		T243	3		T201	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T46	14		T270	1		T166	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T42	11		T140	11		T149	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T19	1		T84	4		T201	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T15	1		T139	2		T261	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T196	12		T172	27		T322	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T52	12		T137	13		T185	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T23	14		T96	10		T49	32
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T265	8		T269	10		T153	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T18	16		T42	8		T238	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T168	10		T237	11		T248	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T67	10		T247	10		T157	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T68	7		T136	9		T162	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T149	5		T244	15		T142	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T139	14		T140	6		T141	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T84	2		T244	4		T206	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T68	10		T137	10		T162	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T21	7		T67	2		T140	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T250	8		T185	7		T245	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T303	1		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T22	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T248	5		T259	16		T292	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T54	8		T201	15		T41	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T62	2		T296	1		T293	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T156	3		T47	1		T185	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T54	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T46	1		T148	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T145	3		T42	16		T243	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T19	1		T197	1		T270	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T15	1		T20	7		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T16	10		T84	15		T196	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T52	16		T137	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T20	13		T249	1		T146	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	1		T52	2		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T18	11		T20	3		T23	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T168	11		T145	10		T265	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	2		T42	10		T150	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T17	11		T136	7		T156	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T6	2		T67	14		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T17	12		T68	9		T139	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T67	1		T84	3		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T68	15		T64	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T21	3		T67	3		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T22	12		T137	1		T196	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14504	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T336	14		T335	11		T187	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T185	7		T277	5		T337	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T54	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T46	14		T248	5		T166	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T42	11		T149	9		T201	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T19	1		T270	1		T245	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T15	1		T140	11		T261	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T84	4		T196	12		T201	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T52	12		T137	13		T139	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T141	15		T172	11		T151	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T260	6		T265	8		T269	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1426	1			T18	16		T23	14		T96	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T168	10		T265	11		T153	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T42	8		T212	12		T154	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T136	9		T237	11		T162	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T67	10		T247	10		T157	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T68	7		T139	14		T141	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T84	2		T244	19		T173	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T68	10		T140	6		T162	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T21	7		T67	2		T140	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T22	11		T137	10		T250	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

auto[0]

4255

1

T15

1

T18

16

T19

1