Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23324

1

T4

20

T5

14

T6

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19984

1

T4

20

T5

14

T6

2

auto[ADC_CTRL_FILTER_COND_OUT]

3340

1

T12

1

T14

2

T15

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17387

1

T4

20

T5

14

T6

2

auto[1]

5937

1

T14

2

T16

10

T18

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19611

1

T4

20

T5

14

T6

2

auto[1]

3713

1

T12

3

T14

2

T16

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	60	1			T163	26		T285	17		T264	16
values[0]	27	1			T338	24		T339	3		-	-
values[1]	499	1			T22	23		T168	21		T156	15
values[2]	550	1			T14	2		T67	25		T160	2
values[3]	751	1			T68	25		T84	19		T156	3
values[4]	664	1			T20	13		T67	5		T62	2
values[5]	702	1			T6	2		T54	9		T238	11
values[6]	752	1			T18	27		T20	7		T239	1
values[7]	701	1			T12	1		T17	11		T137	25
values[8]	764	1			T16	10		T17	12		T21	10
values[9]	3350	1			T15	2		T19	2		T20	3
minimum	14504	1			T4	20		T5	14		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	759	1			T22	23		T67	24		T168	21
values[1]	529	1			T14	2		T67	1		T160	2
values[2]	703	1			T20	13		T68	25		T156	3
values[3]	657	1			T67	5		T62	2		T237	21
values[4]	659	1			T6	2		T239	1		T161	1
values[5]	824	1			T17	11		T18	27		T20	7
values[6]	2858	1			T12	1		T23	15		T68	16
values[7]	782	1			T16	10		T17	12		T19	2
values[8]	873	1			T15	2		T84	5		T47	1
values[9]	151	1			T157	23		T138	1		T240	1
minimum	14529	1			T4	20		T5	14		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

4255

1

T15

1

T18

16

T19

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T241	1		T163	1		T242	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T22	12		T67	11		T168	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T67	1		T160	1		T52	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	2		T160	1		T84	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T20	1		T42	9		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T68	11		T156	1		T243	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T62	2		T145	1		T54	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T67	3		T237	12		T245	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	2		T239	1		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T197	1		T185	19		T142	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T18	17		T20	1		T171	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T17	1		T247	11		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1674	1			T23	15		T68	8		T96	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	1		T137	25		T149	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T17	1		T19	2		T21	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T16	1		T20	1		T136	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T249	1		T196	14		T269	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T15	2		T84	3		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T340	1		T341	1		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T157	12		T138	1		T240	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14422	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T236	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T241	7		T255	3		T155	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T22	11		T67	13		T168	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T52	1		T257	10		T165	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T84	14		T164	11		T258	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T20	12		T42	9		T139	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T68	14		T156	2		T243	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T145	2		T42	15		T238	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T67	2		T237	9		T222	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T185	7		T158	13		T201	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T185	17		T260	16		T282	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T18	10		T20	6		T171	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T17	10		T212	9		T248	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	852	1			T68	8		T159	10		T144	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T149	4		T261	10		T266	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T17	11		T21	2		T52	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T16	9		T20	2		T136	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T196	3		T269	16		T283	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T84	2		T250	9		T262	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T340	13		T341	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T157	11		T287	11		T264	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T12	3		T14	2		T97	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T285	17		T342	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T163	13		T264	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T339	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T338	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T46	15		T163	1		T242	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T22	12		T168	11		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T67	1		T160	1		T52	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	2		T67	11		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T148	1		T140	7		T265	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T68	11		T84	5		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T20	1		T62	2		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T67	3		T265	9		T206	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	2		T54	9		T238	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T197	1		T185	19		T142	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T18	17		T20	1		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T247	11		T138	1		T150	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T146	2		T140	14		T149	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	1		T17	1		T137	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T17	1		T21	8		T68	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T16	1		T136	10		T149	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1839	1			T19	2		T23	15		T96	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T15	2		T20	1		T84	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14409	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T163	13		T264	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T339	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T338	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T254	11		T155	9		T256	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T22	11		T168	10		T156	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T52	1		T257	10		T241	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T67	13		T201	18		T164	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T242	8		T268	2		T282	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T68	14		T84	14		T156	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T20	12		T145	2		T42	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T67	2		T206	15		T328	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T238	4		T139	5		T185	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T185	17		T260	10		T222	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T18	10		T20	6		T158	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T260	6		T248	9		T202	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T149	10		T244	2		T270	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T17	10		T261	10		T212	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T17	11		T21	2		T68	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T16	9		T136	6		T149	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T159	10		T144	20		T55	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T20	2		T84	2		T157	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T241	8		T163	1		T242	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T22	12		T67	14		T168	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T67	1		T160	1		T52	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	2		T160	1		T84	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T20	13		T42	10		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T68	15		T156	3		T243	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T62	2		T145	3		T54	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T67	3		T237	10		T245	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	2		T239	1		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T197	1		T185	18		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T18	11		T20	7		T171	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T17	11		T247	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1180	1			T23	1		T68	9		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	1		T137	2		T149	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T17	12		T19	1		T21	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T16	10		T20	3		T136	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T249	1		T196	5		T269	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T15	1		T84	3		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T340	14		T341	12		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T157	12		T138	1		T240	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14516	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T236	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T271	8		T267	5		T110	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T22	11		T67	10		T168	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T46	14		T140	6		T257	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T84	4		T141	2		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T42	8		T139	14		T141	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T68	10		T142	16		T162	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T54	8		T42	11		T238	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T67	2		T237	11		T245	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T185	7		T158	12		T201	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T185	18		T142	2		T260	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T18	16		T201	6		T311	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T247	10		T212	12		T248	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T23	14		T68	7		T96	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T137	23		T149	5		T261	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T19	1		T21	7		T52	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T136	9		T248	5		T273	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T196	12		T269	14		T277	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T15	1		T84	2		T140	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T157	11		T274	10		T264	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T254	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T285	1		T342	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T163	14		T264	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T339	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T338	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T46	1		T163	1		T242	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T22	12		T168	11		T156	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T67	1		T160	1		T52	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	2		T67	14		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T148	1		T140	1		T265	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T68	15		T84	15		T156	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T20	13		T62	2		T145	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T67	3		T265	1		T206	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	2		T54	1		T238	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T197	1		T185	18		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T18	11		T20	7		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T247	1		T138	1		T150	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T146	2		T140	1		T149	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	1		T17	11		T137	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T17	12		T21	3		T68	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	10		T136	7		T149	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T19	1		T23	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T15	1		T20	3		T84	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14504	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T285	16		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T163	12		T264	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T338	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T46	14		T271	8		T254	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T22	11		T168	10		T172	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T257	9		T277	11		T324	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T67	10		T141	2		T201	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T140	6		T265	11		T268	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T68	10		T84	4		T237	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T42	19		T139	14		T141	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T67	2		T265	8		T206	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T54	8		T238	6		T139	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T185	18		T142	2		T260	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T18	16		T158	12		T201	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T247	10		T260	6		T248	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T140	13		T149	9		T244	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T137	23		T261	14		T212	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T21	7		T68	7		T52	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T136	9		T149	5		T172	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1482	1			T19	1		T23	14		T96	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T15	1		T84	2		T157	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

auto[0]

4255

1

T15

1

T18

16

T19

1