Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23324

1

T4

20

T5

14

T6

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19879

1

T4

20

T5

14

T6

2

auto[ADC_CTRL_FILTER_COND_OUT]

3445

1

T12

1

T18

27

T19

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17324

1

T4

20

T5

14

T6

2

auto[1]

6000

1

T12

1

T60

1

T14

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19611

1

T4

20

T5

14

T6

2

auto[1]

3713

1

T12

3

T14

2

T16

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	572	1			T12	1		T60	1		T14	1
values[0]	24	1			T210	24		-	-		-	-
values[1]	495	1			T14	2		T15	2		T17	11
values[2]	2977	1			T18	27		T23	15		T96	11
values[3]	723	1			T12	1		T22	23		T62	2
values[4]	524	1			T68	25		T161	1		T148	1
values[5]	591	1			T16	10		T67	24		T84	19
values[6]	888	1			T67	6		T52	28		T157	23
values[7]	509	1			T20	7		T68	16		T237	21
values[8]	645	1			T17	12		T21	10		T46	15
values[9]	1180	1			T6	2		T19	2		T20	16
minimum	14196	1			T4	20		T5	14		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	555	1			T14	2		T15	2		T17	11
values[1]	3016	1			T12	1		T18	27		T23	15
values[2]	658	1			T22	23		T160	1		T145	10
values[3]	434	1			T68	25		T84	19		T148	1
values[4]	750	1			T16	10		T67	25		T42	27
values[5]	828	1			T67	5		T68	16		T145	3
values[6]	441	1			T20	7		T237	21		T46	15
values[7]	740	1			T17	12		T21	10		T137	25
values[8]	1059	1			T6	2		T19	2		T20	16
values[9]	154	1			T84	5		T244	7		T257	20
minimum	14689	1			T4	20		T5	14		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

4255

1

T15

1

T18

16

T19

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	2		T15	2		T17	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T146	2		T279	1		T245	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1642	1			T23	15		T96	11		T62	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T12	1		T18	17		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T171	2		T269	1		T282	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T22	12		T160	1		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T150	1		T260	7		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T68	11		T84	5		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T16	1		T67	11		T247	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T67	1		T42	12		T139	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T67	3		T145	1		T52	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T68	8		T54	9		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T47	1		T238	7		T196	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T20	1		T237	12		T46	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T17	1		T21	8		T137	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T137	14		T236	1		T248	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T6	2		T138	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T19	2		T20	2		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T84	3		T254	13		T348	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T244	5		T257	10		T265	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14463	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T249	1		T255	12		T288	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T17	10		T168	10		T42	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T242	8		T165	1		T281	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	844	1			T159	10		T144	20		T55	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T18	10		T244	14		T201	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T171	1		T269	1		T282	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T22	11		T145	9		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T150	14		T260	6		T202	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T68	14		T84	14		T268	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T16	9		T67	13		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T42	15		T139	5		T151	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T67	2		T145	2		T52	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T68	8		T261	10		T185	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T238	4		T196	2		T311	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T20	6		T237	9		T149	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T17	11		T21	2		T152	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T248	11		T315	20		T151	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T248	4		T290	12		T166	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T20	14		T136	6		T156	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T84	2		T254	11		T348	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T244	2		T257	10		T349	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	3		T14	2		T97	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T255	13		T210	11		T204	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	411	1			T12	1		T60	1		T14	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T236	1		T206	11		T319	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T210	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	2		T15	2		T17	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T249	1		T146	2		T279	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1626	1			T23	15		T96	11		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T18	17		T246	1		T201	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T62	2		T140	14		T171	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	1		T22	12		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T260	7		T269	12		T286	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T68	11		T161	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T16	1		T67	11		T247	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T84	5		T42	12		T139	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T67	3		T52	13		T157	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T67	1		T261	15		T185	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T145	1		T47	1		T238	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T20	1		T68	8		T237	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T17	1		T21	8		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T46	15		T137	14		T149	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	363	1			T6	2		T137	11		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T19	2		T20	2		T160	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14101	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T84	2		T254	11		T319	23
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T206	5		T319	4		T191	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T210	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T17	10		T168	10		T42	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T165	1		T255	13		T317	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	817	1			T159	10		T144	20		T55	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T18	10		T201	8		T242	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T171	1		T158	13		T282	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T22	11		T145	9		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T260	6		T269	12		T242	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T68	14		T268	2		T153	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T16	9		T67	13		T150	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T84	14		T42	15		T139	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T67	2		T52	15		T157	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T261	10		T185	17		T241	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T145	2		T238	4		T196	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T20	6		T68	8		T237	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T17	11		T21	2		T152	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T149	4		T248	11		T283	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T248	4		T290	12		T166	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T20	14		T136	6		T156	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	3		T14	2		T97	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T14	2		T15	1		T17	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T146	2		T279	1		T245	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1168	1			T23	1		T96	1		T62	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T12	1		T18	11		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T171	3		T269	2		T282	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T22	12		T160	1		T145	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T150	15		T260	7		T202	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T68	15		T84	15		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T16	10		T67	14		T247	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T67	1		T42	16		T139	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T67	3		T145	3		T52	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T68	9		T54	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T47	1		T238	5		T196	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T20	7		T237	10		T46	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T17	12		T21	3		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T137	1		T236	1		T248	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T6	2		T138	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T19	1		T20	16		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T84	3		T254	12		T348	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T244	3		T257	11		T265	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14546	1			T4	20		T5	14		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T249	1		T255	14		T288	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T15	1		T168	10		T42	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T245	13		T165	1		T271	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T23	14		T96	10		T49	32
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T18	16		T244	15		T201	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T173	6		T347	6		T350	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T22	11		T140	11		T212	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T260	6		T269	10		T222	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T68	10		T84	4		T268	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T67	10		T247	10		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T42	11		T139	2		T151	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T67	2		T52	12		T260	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T68	7		T54	8		T261	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T238	6		T196	12		T140	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T237	11		T46	14		T149	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T21	7		T137	10		T337	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T137	13		T248	2		T315	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T248	5		T245	15		T290	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T19	1		T136	9		T139	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T84	2		T254	12		T348	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T244	4		T257	9		T265	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T102	1		T175	6		T351	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T255	11		T288	11		T210	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	420	1			T12	1		T60	1		T14	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T236	1		T206	6		T319	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T210	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T14	2		T15	1		T17	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T249	1		T146	2		T279	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1143	1			T23	1		T96	1		T159	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T18	11		T246	1		T201	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T62	2		T140	1		T171	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	1		T22	12		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T260	7		T269	14		T286	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T68	15		T161	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T16	10		T67	14		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T84	15		T42	16		T139	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T67	3		T52	16		T157	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T67	1		T261	11		T185	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T145	3		T47	1		T238	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T20	7		T68	9		T237	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T17	12		T21	3		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T46	1		T137	1		T149	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T6	2		T137	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T19	1		T20	16		T160	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14196	1			T4	20		T5	14		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T84	2		T254	12		T319	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T206	10		T319	13		T178	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T210	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T168	10		T42	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T245	13		T165	1		T255	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T23	14		T96	10		T49	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T18	16		T201	6		T166	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T140	13		T158	12		T173	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T22	11		T140	11		T212	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T260	6		T269	10		T222	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T68	10		T268	9		T153	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T67	10		T247	10		T172	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T84	4		T42	11		T139	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T67	2		T52	12		T157	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T261	14		T185	18		T201	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T238	6		T196	12		T140	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T68	7		T237	11		T54	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T21	7		T273	14		T110	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T46	14		T137	13		T149	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T137	10		T248	5		T245	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T19	1		T136	9		T139	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19069

1

T4

20

T5

14

T6

2

auto[1]

auto[0]

4255

1

T15

1

T18

16

T19

1