Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5863	1			T2	10		T4	6		T5	20
testmodes[AdcCtrlTestmodeNormal]	4700	1			T2	10		T3	2		T4	7
testmodes[AdcCtrlTestmodeLowpower]	4999	1			T7	17		T8	2		T13	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3017	1			T2	6		T4	3		T5	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1475	1			T2	4		T4	3		T10	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1258	1			T14	1		T18	1		T60	21
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1480	1			T2	4		T4	2		T10	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1640	1			T2	5		T3	1		T4	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1239	1			T8	1		T14	1		T18	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1258	1			T18	1		T49	1		T60	19
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1236	1			T8	1		T14	2		T18	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2261	1			T7	16		T14	2		T38	12