Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.76	99.07	96.67	100.00	100.00	98.83	98.33	91.42

Total tests in report: 919

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
72.97	72.97	97.75	97.75	81.97	81.97	88.03	88.03	48.65	48.65	96.48	96.48	85.98	85.98	11.93	11.93	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.882870214
80.08	7.11	98.49	0.74	86.83	4.86	96.09	8.06	72.97	24.32	97.96	1.48	91.49	5.51	16.75	4.82	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.110937521
82.97	2.89	98.49	0.00	86.83	0.00	96.09	0.00	86.49	13.51	97.96	0.00	91.49	0.00	23.48	6.74	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.1368959207
85.47	2.50	98.67	0.19	92.59	5.76	96.09	0.00	86.49	0.00	98.33	0.37	94.49	3.01	31.64	8.16	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.802382470
87.07	1.59	98.70	0.03	92.59	0.00	96.09	0.00	97.30	10.81	98.39	0.06	94.49	0.00	31.89	0.25	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.2841161129
88.17	1.10	98.70	0.00	93.08	0.49	96.09	0.00	97.30	0.00	98.39	0.00	94.49	0.00	39.13	7.24	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.1894260604
89.02	0.85	98.70	0.00	93.08	0.00	96.09	0.00	97.30	0.00	98.39	0.00	94.66	0.17	44.95	5.81	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.2967525396
89.81	0.79	98.70	0.00	93.12	0.04	96.09	0.00	100.00	2.70	98.39	0.00	94.66	0.00	47.72	2.77	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2535091286
90.59	0.78	98.70	0.00	93.12	0.00	96.09	0.00	100.00	0.00	98.39	0.00	95.16	0.50	52.66	4.94	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.4033215602
91.23	0.64	98.77	0.06	94.03	0.91	96.92	0.83	100.00	0.00	98.52	0.12	95.49	0.33	54.85	2.20	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1094347849
91.84	0.61	98.77	0.00	94.03	0.00	96.92	0.00	100.00	0.00	98.52	0.00	95.49	0.00	59.15	4.29	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.1068260737
92.37	0.53	98.77	0.00	94.03	0.00	96.92	0.00	100.00	0.00	98.52	0.00	95.49	0.00	62.84	3.69	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.385475463
92.85	0.49	98.80	0.03	94.20	0.16	99.29	2.37	100.00	0.00	98.58	0.06	96.16	0.67	62.96	0.12	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.261542441
93.31	0.45	98.80	0.00	95.51	1.32	99.76	0.47	100.00	0.00	98.64	0.06	96.83	0.67	63.61	0.65	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1658727620
93.72	0.41	98.80	0.00	95.51	0.00	99.76	0.00	100.00	0.00	98.64	0.00	96.83	0.00	66.51	2.89	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.1724010478
94.10	0.38	98.80	0.00	95.51	0.00	99.76	0.00	100.00	0.00	98.64	0.00	96.83	0.00	69.18	2.67	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.2358821102
94.41	0.30	98.92	0.12	95.64	0.12	99.76	0.00	100.00	0.00	98.70	0.06	96.83	0.00	71.00	1.82	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.4227129939
94.68	0.27	98.92	0.00	95.64	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.83	0.00	72.92	1.92	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.2377243826
94.92	0.24	98.92	0.00	95.64	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.83	0.00	74.62	1.70	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.4270390387
95.14	0.21	98.92	0.00	95.64	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.83	0.00	76.12	1.50	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.562452818
95.33	0.19	98.92	0.00	95.64	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.16	1.34	76.12	0.00	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2121579234
95.49	0.16	98.92	0.00	95.64	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.16	0.00	77.24	1.12	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.3216030578
95.64	0.15	98.92	0.00	95.64	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.16	0.00	78.31	1.07	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.4112496449
95.78	0.14	98.92	0.00	95.64	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.16	0.00	79.26	0.95	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.3553418896
95.90	0.12	98.92	0.00	95.64	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.16	0.00	80.08	0.82	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.438928991
96.01	0.11	98.92	0.00	95.64	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.33	0.17	80.71	0.62	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup.1910191850
96.11	0.10	98.92	0.00	95.64	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.33	0.00	81.43	0.72	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_both.2584959317
96.21	0.10	98.92	0.00	95.64	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.33	0.00	82.11	0.67	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_clock_gating.567265857
96.30	0.09	98.92	0.00	95.64	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.33	0.00	82.73	0.62	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.2736636748
96.38	0.08	98.92	0.00	95.76	0.12	99.76	0.00	100.00	0.00	98.70	0.00	98.33	0.00	83.15	0.42	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.720886218
96.45	0.07	98.92	0.00	95.76	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.33	0.00	83.68	0.52	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.371266774
96.52	0.07	98.92	0.00	96.05	0.29	99.76	0.00	100.00	0.00	98.70	0.00	98.33	0.00	83.88	0.20	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3999770745
96.58	0.06	99.01	0.09	96.17	0.12	100.00	0.24	100.00	0.00	98.70	0.00	98.33	0.00	83.88	0.00	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.1687789569
96.65	0.06	99.01	0.00	96.17	0.00	100.00	0.00	100.00	0.00	98.70	0.00	98.33	0.00	84.33	0.45	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.326460324
96.71	0.06	99.07	0.06	96.42	0.25	100.00	0.00	100.00	0.00	98.83	0.12	98.33	0.00	84.33	0.00	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4141464110
96.77	0.06	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	84.75	0.42	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.1895175841
96.83	0.06	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	85.18	0.42	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_clock_gating.3443848357
96.88	0.05	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	85.53	0.35	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.1347557212
96.93	0.05	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	85.85	0.32	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.1323414069
96.97	0.04	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	86.15	0.30	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup.308742742
97.01	0.04	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	86.45	0.30	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.4096975790
97.05	0.04	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	86.72	0.27	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3895472511
97.09	0.04	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	87.00	0.27	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_clock_gating.3195752565
97.13	0.04	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	87.25	0.25	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.911057519
97.16	0.04	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	87.50	0.25	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2943038010
97.20	0.03	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	87.72	0.22	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2479745404
97.23	0.03	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	87.95	0.22	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.254759105
97.26	0.03	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.15	0.20	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all.2769429961
97.28	0.02	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.32	0.17	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.1017372125
97.31	0.02	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.50	0.17	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all.2750798407
97.33	0.02	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.67	0.17	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt.1055708455
97.35	0.02	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.82	0.15	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.4081190971
97.37	0.02	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	88.97	0.15	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_clock_gating.1964242751
97.40	0.02	99.07	0.00	96.42	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.12	0.15	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt.826772388
97.42	0.02	99.07	0.00	96.54	0.12	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.14	0.02	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.1504962768
97.43	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.27	0.12	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.3497927828
97.45	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.39	0.12	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.63958427
97.47	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.52	0.12	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.2824421629
97.49	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.64	0.12	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_both.3656299847
97.50	0.02	99.07	0.00	96.62	0.08	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.67	0.02	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1165662148
97.52	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.77	0.10	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.877891769
97.53	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.87	0.10	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt.1128941004
97.55	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	89.97	0.10	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup.2348048208
97.56	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.07	0.10	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2199111748
97.57	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.14	0.07	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.2260330150
97.58	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.22	0.07	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_clock_gating.3703948261
97.59	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.29	0.07	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2819299886
97.60	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.37	0.07	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_clock_gating.1921394534
97.61	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.44	0.07	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1601818202
97.62	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.52	0.07	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all.4148301311
97.64	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.59	0.07	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_clock_gating.56451080
97.65	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.67	0.07	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.297449106
97.65	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.72	0.05	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.352085343
97.66	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.77	0.05	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.1759991229
97.67	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.82	0.05	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.3959534631
97.67	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.87	0.05	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled.3238102012
97.68	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.92	0.05	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled.843590067
97.69	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	90.97	0.05	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled.1084760183
97.70	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.02	0.05	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1620987031
97.70	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.07	0.05	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled.3102030893
97.71	0.01	99.07	0.00	96.67	0.04	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.07	0.00	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2415336544
97.71	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.09	0.02	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.2191717228
97.72	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.12	0.02	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3185401622
97.72	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.14	0.02	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.2082356345
97.72	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.17	0.02	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup.1534862069
97.73	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.19	0.02	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.748295309
97.73	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.22	0.02	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.3300648722
97.73	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.24	0.02	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt.849537607
97.74	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.27	0.02	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_fsm_reset.3313653821
97.74	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.29	0.02	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_fsm_reset.3653870262
97.74	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.32	0.02	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_both.285479830
97.75	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.34	0.02	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_clock_gating.288740534
97.75	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.37	0.02	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup.3474186692
97.76	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.39	0.02	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2847737994
97.76	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.83	0.00	98.33	0.00	91.42	0.02	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.2979016805

---

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.672946484
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2898305423
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3333021528
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.2813120008
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1836975861
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3538220461
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.4223472701
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3142608023
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1563116289
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.153168766
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2362337114
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4080303933
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.2396225321
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.869981617
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1443751737
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.4248083246
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2625153873
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.4145308459
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3518719796
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4085817345
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4114820883
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3388133652
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.653726997
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1413207605
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2152363593
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3293270219
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2092577361
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1956670916
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.3662392243
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.309881636
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.615882053
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2858234457
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.904655637
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.636008325
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.4014839420
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1734014208
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2678150388
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.617051841
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3988728844
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2707827203
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2796894181
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2657843345
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3725237776
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1524923851
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.176251375
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.4168227651
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.4115347030
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.252216639
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1009289916
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2627858104
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.107162429
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2416892649
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.2624745299
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1315469500
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3593798828
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1709139716
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1112952569
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2382996212
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.488731297
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1107630953
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2057965993
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1756584753
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2289866390
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2015156137
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.401641725
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1830636745
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4187068288
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1055618387
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.520144773
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.926806321
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.859899984
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2197511116
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3558145027
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3039972591
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/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3243924720
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.1088579642
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.3592010172
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.1506708226
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.2947863945
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.557126021
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.757021141
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.2371634700
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.350959213
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1687687889
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.1864898180
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.921775204
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.944003316
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.3186536457
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.1705450471
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.218998028

---

Total test records in report: 919

---

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

---

TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.1687789569			Aug 28 08:12:13 PM UTC 24	Aug 28 08:12:16 PM UTC 24	480594403 ps
T2	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.1504962768			Aug 28 08:12:11 PM UTC 24	Aug 28 08:12:17 PM UTC 24	5703901568 ps
T3	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3936049292			Aug 28 08:12:12 PM UTC 24	Aug 28 08:12:21 PM UTC 24	3526027893 ps
T4	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.3388921658			Aug 28 08:12:22 PM UTC 24	Aug 28 08:12:27 PM UTC 24	3755356457 ps
T5	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.3491688762			Aug 28 08:12:07 PM UTC 24	Aug 28 08:12:28 PM UTC 24	5541124473 ps
T6	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.1469406767			Aug 28 08:12:15 PM UTC 24	Aug 28 08:12:30 PM UTC 24	6139693779 ps
T7	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.1743275783			Aug 28 08:12:11 PM UTC 24	Aug 28 08:12:31 PM UTC 24	36281631855 ps
T21	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.261542441			Aug 28 08:12:12 PM UTC 24	Aug 28 08:12:33 PM UTC 24	4151541313 ps
T22	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.947717143			Aug 28 08:12:31 PM UTC 24	Aug 28 08:12:33 PM UTC 24	509738009 ps
T8	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.882870214			Aug 28 08:12:27 PM UTC 24	Aug 28 08:12:35 PM UTC 24	26229715755 ps
T9	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.3262022700			Aug 28 08:12:33 PM UTC 24	Aug 28 08:12:38 PM UTC 24	5653513449 ps
T10	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.1278528939			Aug 28 08:12:49 PM UTC 24	Aug 28 08:12:57 PM UTC 24	2904502740 ps
T23	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.2158179728			Aug 28 08:12:29 PM UTC 24	Aug 28 08:13:02 PM UTC 24	7902656032 ps
T11	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.3364614012			Aug 28 08:13:05 PM UTC 24	Aug 28 08:13:12 PM UTC 24	6442271639 ps
T24	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.168619147			Aug 28 08:13:10 PM UTC 24	Aug 28 08:13:12 PM UTC 24	430963781 ps
T25	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.3291427233			Aug 28 08:13:08 PM UTC 24	Aug 28 08:13:15 PM UTC 24	4045192035 ps
T26	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.2650649902			Aug 28 08:13:12 PM UTC 24	Aug 28 08:13:16 PM UTC 24	6052944224 ps
T12	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1094347849			Aug 28 08:12:10 PM UTC 24	Aug 28 08:13:34 PM UTC 24	484221777364 ps
T27	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.730637805			Aug 28 08:13:35 PM UTC 24	Aug 28 08:13:41 PM UTC 24	5185314483 ps
T13	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.52866837			Aug 28 08:12:10 PM UTC 24	Aug 28 08:13:41 PM UTC 24	176119408177 ps
T14	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.110937521			Aug 28 08:13:03 PM UTC 24	Aug 28 08:13:43 PM UTC 24	37302249506 ps
T37	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.2357633132			Aug 28 08:13:43 PM UTC 24	Aug 28 08:13:46 PM UTC 24	562857720 ps
T38	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.3483751680			Aug 28 08:12:25 PM UTC 24	Aug 28 08:13:49 PM UTC 24	30750141684 ps
T39	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.2449114790			Aug 28 08:12:58 PM UTC 24	Aug 28 08:13:51 PM UTC 24	27897267575 ps
T40	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1229258336			Aug 28 08:13:41 PM UTC 24	Aug 28 08:14:02 PM UTC 24	2534359918 ps
T41	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.3194191946			Aug 28 08:13:45 PM UTC 24	Aug 28 08:14:07 PM UTC 24	5936528170 ps
T42	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.1612282996			Aug 28 08:13:37 PM UTC 24	Aug 28 08:14:10 PM UTC 24	40564865273 ps
T43	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.3678839916			Aug 28 08:13:41 PM UTC 24	Aug 28 08:14:16 PM UTC 24	8145812147 ps
T44	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.925898594			Aug 28 08:14:07 PM UTC 24	Aug 28 08:14:16 PM UTC 24	2970407733 ps
T15	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.829383338			Aug 28 08:12:39 PM UTC 24	Aug 28 08:14:22 PM UTC 24	179926049724 ps
T391	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.436367704			Aug 28 08:14:23 PM UTC 24	Aug 28 08:14:25 PM UTC 24	545993420 ps
T16	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.3533550890			Aug 28 08:13:15 PM UTC 24	Aug 28 08:14:28 PM UTC 24	162066207695 ps
T80	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.589380512			Aug 28 08:14:17 PM UTC 24	Aug 28 08:14:40 PM UTC 24	8090209105 ps
T159	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.4081291399			Aug 28 08:14:26 PM UTC 24	Aug 28 08:14:55 PM UTC 24	5742275226 ps
T17	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.4056358286			Aug 28 08:12:34 PM UTC 24	Aug 28 08:14:55 PM UTC 24	161565649642 ps
T18	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2535091286			Aug 28 08:14:17 PM UTC 24	Aug 28 08:14:56 PM UTC 24	79628749164 ps
T160	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.1220139133			Aug 28 08:14:10 PM UTC 24	Aug 28 08:15:08 PM UTC 24	45696747163 ps
T161	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.871985700			Aug 28 08:15:09 PM UTC 24	Aug 28 08:15:16 PM UTC 24	4942961241 ps
T162	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.1500892260			Aug 28 08:15:33 PM UTC 24	Aug 28 08:15:36 PM UTC 24	385390619 ps
T19	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.802382470			Aug 28 08:13:50 PM UTC 24	Aug 28 08:15:44 PM UTC 24	331503639653 ps
T147	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.4209971352			Aug 28 08:15:36 PM UTC 24	Aug 28 08:15:52 PM UTC 24	6060156322 ps
T20	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1620232814			Aug 28 08:15:17 PM UTC 24	Aug 28 08:15:54 PM UTC 24	69715571495 ps
T47	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.2272004094			Aug 28 08:12:07 PM UTC 24	Aug 28 08:15:59 PM UTC 24	331086070932 ps
T52	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.2625747779			Aug 28 08:12:10 PM UTC 24	Aug 28 08:16:10 PM UTC 24	165118748736 ps
T148	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.1426320766			Aug 28 08:15:12 PM UTC 24	Aug 28 08:16:15 PM UTC 24	40777589944 ps
T53	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.1323414069			Aug 28 08:12:22 PM UTC 24	Aug 28 08:16:24 PM UTC 24	332514747077 ps
T149	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.904717779			Aug 28 08:16:24 PM UTC 24	Aug 28 08:16:28 PM UTC 24	2791317546 ps
T81	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.115350115			Aug 28 08:13:13 PM UTC 24	Aug 28 08:16:33 PM UTC 24	165896667416 ps
T150	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.720886218			Aug 28 08:12:15 PM UTC 24	Aug 28 08:16:35 PM UTC 24	322289984630 ps
T48	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1991258987			Aug 28 08:16:35 PM UTC 24	Aug 28 08:16:50 PM UTC 24	2752067988 ps
T163	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.32846371			Aug 28 08:13:13 PM UTC 24	Aug 28 08:16:54 PM UTC 24	160366167416 ps
T172	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.1783769176			Aug 28 08:16:55 PM UTC 24	Aug 28 08:16:57 PM UTC 24	355952453 ps
T156	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.3500336381			Aug 28 08:12:17 PM UTC 24	Aug 28 08:17:07 PM UTC 24	324606470788 ps
T151	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.3912590480			Aug 28 08:13:45 PM UTC 24	Aug 28 08:17:07 PM UTC 24	166847050319 ps
T173	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.419834986			Aug 28 08:16:58 PM UTC 24	Aug 28 08:17:16 PM UTC 24	6017492466 ps
T54	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.221013578			Aug 28 08:14:57 PM UTC 24	Aug 28 08:17:22 PM UTC 24	184682919954 ps
T141	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1322584257			Aug 28 08:15:55 PM UTC 24	Aug 28 08:17:43 PM UTC 24	326423606715 ps
T157	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.4096975790			Aug 28 08:15:53 PM UTC 24	Aug 28 08:17:47 PM UTC 24	160328650815 ps
T164	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.2294333758			Aug 28 08:12:10 PM UTC 24	Aug 28 08:17:48 PM UTC 24	163658414759 ps
T183	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.3982543201			Aug 28 08:17:45 PM UTC 24	Aug 28 08:17:51 PM UTC 24	4096286289 ps
T184	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.929969734			Aug 28 08:16:29 PM UTC 24	Aug 28 08:18:03 PM UTC 24	39516714859 ps
T49	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1074381201			Aug 28 08:17:52 PM UTC 24	Aug 28 08:18:10 PM UTC 24	7364333158 ps
T185	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.1762220272			Aug 28 08:17:48 PM UTC 24	Aug 28 08:18:10 PM UTC 24	42386672646 ps
T186	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.1644030606			Aug 28 08:18:11 PM UTC 24	Aug 28 08:18:13 PM UTC 24	377218445 ps
T187	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.2340647382			Aug 28 08:12:09 PM UTC 24	Aug 28 08:18:14 PM UTC 24	167610733543 ps
T392	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.602318009			Aug 28 08:18:11 PM UTC 24	Aug 28 08:18:15 PM UTC 24	5944032366 ps
T248	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.4097283872			Aug 28 08:13:52 PM UTC 24	Aug 28 08:18:38 PM UTC 24	169758978173 ps
T221	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.669127021			Aug 28 08:14:06 PM UTC 24	Aug 28 08:18:41 PM UTC 24	254729339722 ps
T158	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.228939775			Aug 28 08:18:14 PM UTC 24	Aug 28 08:18:46 PM UTC 24	164699974845 ps
T393	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3116619407			Aug 28 08:12:39 PM UTC 24	Aug 28 08:18:50 PM UTC 24	164512247894 ps
T193	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3884878998			Aug 28 08:17:17 PM UTC 24	Aug 28 08:18:50 PM UTC 24	166102070545 ps
T394	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.766544891			Aug 28 08:18:52 PM UTC 24	Aug 28 08:19:03 PM UTC 24	4525120437 ps
T395	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.3017419278			Aug 28 08:15:45 PM UTC 24	Aug 28 08:19:14 PM UTC 24	162141979802 ps
T396	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.3769056933			Aug 28 08:17:08 PM UTC 24	Aug 28 08:19:23 PM UTC 24	171102351310 ps
T50	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3243924720			Aug 28 08:19:24 PM UTC 24	Aug 28 08:19:54 PM UTC 24	78394684580 ps
T135	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2479745404			Aug 28 08:12:10 PM UTC 24	Aug 28 08:19:56 PM UTC 24	620919348563 ps
T397	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.2615406946			Aug 28 08:19:57 PM UTC 24	Aug 28 08:20:01 PM UTC 24	408824629 ps
T398	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.3186536457			Aug 28 08:20:01 PM UTC 24	Aug 28 08:20:10 PM UTC 24	5662309347 ps
T399	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1111350052			Aug 28 08:14:42 PM UTC 24	Aug 28 08:20:11 PM UTC 24	335197264999 ps
T60	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.3497927828			Aug 28 08:12:26 PM UTC 24	Aug 28 08:20:14 PM UTC 24	127276407844 ps
T55	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.2841161129			Aug 28 08:12:11 PM UTC 24	Aug 28 08:20:21 PM UTC 24	63154866707 ps
T136	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.4033215602			Aug 28 08:14:55 PM UTC 24	Aug 28 08:20:23 PM UTC 24	537073403848 ps
T205	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.511592045			Aug 28 08:19:04 PM UTC 24	Aug 28 08:20:24 PM UTC 24	44458303548 ps
T206	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.2568829755			Aug 28 08:13:16 PM UTC 24	Aug 28 08:20:28 PM UTC 24	167414093202 ps
T137	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.1894260604			Aug 28 08:12:20 PM UTC 24	Aug 28 08:20:29 PM UTC 24	550716848127 ps
T139	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.2492374630			Aug 28 08:16:00 PM UTC 24	Aug 28 08:20:31 PM UTC 24	384394395710 ps
T207	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.944003316			Aug 28 08:20:32 PM UTC 24	Aug 28 08:20:48 PM UTC 24	3269936283 ps
T208	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.398530238			Aug 28 08:17:08 PM UTC 24	Aug 28 08:20:52 PM UTC 24	165498089961 ps
T140	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.4002865262			Aug 28 08:12:09 PM UTC 24	Aug 28 08:21:03 PM UTC 24	162352399020 ps
T209	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.2360216037			Aug 28 08:12:16 PM UTC 24	Aug 28 08:21:04 PM UTC 24	164218945591 ps
T210	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.1088579642			Aug 28 08:21:05 PM UTC 24	Aug 28 08:21:09 PM UTC 24	301344077 ps
T400	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.921775204			Aug 28 08:20:49 PM UTC 24	Aug 28 08:21:14 PM UTC 24	22955801304 ps
T401	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.1833645207			Aug 28 08:21:09 PM UTC 24	Aug 28 08:21:15 PM UTC 24	5820274715 ps
T51	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.218998028			Aug 28 08:20:52 PM UTC 24	Aug 28 08:21:20 PM UTC 24	4421077567 ps
T402	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.3354304556			Aug 28 08:12:34 PM UTC 24	Aug 28 08:21:20 PM UTC 24	328970712480 ps
T138	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.1522132472			Aug 28 08:17:38 PM UTC 24	Aug 28 08:21:24 PM UTC 24	519228240986 ps
T252	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2206387486			Aug 28 08:12:18 PM UTC 24	Aug 28 08:21:28 PM UTC 24	402308252239 ps
T142	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.757021141			Aug 28 08:20:10 PM UTC 24	Aug 28 08:21:42 PM UTC 24	164902789229 ps
T403	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.4256944918			Aug 28 08:12:17 PM UTC 24	Aug 28 08:21:55 PM UTC 24	164405703475 ps
T143	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1785518683			Aug 28 08:18:36 PM UTC 24	Aug 28 08:21:56 PM UTC 24	491945637492 ps
T404	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.4192047695			Aug 28 08:21:57 PM UTC 24	Aug 28 08:22:02 PM UTC 24	2856481103 ps
T405	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.1861528894			Aug 28 08:14:29 PM UTC 24	Aug 28 08:22:07 PM UTC 24	325508086032 ps
T188	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.3592010172			Aug 28 08:20:29 PM UTC 24	Aug 28 08:22:10 PM UTC 24	163639366454 ps
T222	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.4101624896			Aug 28 08:15:43 PM UTC 24	Aug 28 08:22:35 PM UTC 24	486876704820 ps
T406	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.267120126			Aug 28 08:22:37 PM UTC 24	Aug 28 08:22:39 PM UTC 24	473422273 ps
T56	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.1368959207			Aug 28 08:12:12 PM UTC 24	Aug 28 08:22:41 PM UTC 24	415199759969 ps
T144	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.1920740934			Aug 28 08:13:59 PM UTC 24	Aug 28 08:22:49 PM UTC 24	166640469376 ps
T407	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.2465908489			Aug 28 08:22:41 PM UTC 24	Aug 28 08:22:55 PM UTC 24	5799720272 ps
T174	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.1226840675			Aug 28 08:13:29 PM UTC 24	Aug 28 08:23:06 PM UTC 24	342112198007 ps
T194	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.557126021			Aug 28 08:20:21 PM UTC 24	Aug 28 08:23:08 PM UTC 24	328364538353 ps
T145	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.4257163092			Aug 28 08:21:15 PM UTC 24	Aug 28 08:23:08 PM UTC 24	327603425616 ps
T146	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.3401791434			Aug 28 08:14:57 PM UTC 24	Aug 28 08:23:22 PM UTC 24	176994581426 ps
T220	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.1895175841			Aug 28 08:12:28 PM UTC 24	Aug 28 08:23:23 PM UTC 24	332050995480 ps
T28	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.486307072			Aug 28 08:22:11 PM UTC 24	Aug 28 08:23:24 PM UTC 24	244228177562 ps
T408	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.2551446193			Aug 28 08:23:25 PM UTC 24	Aug 28 08:23:28 PM UTC 24	3411945203 ps
T189	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.2260330150			Aug 28 08:21:43 PM UTC 24	Aug 28 08:23:33 PM UTC 24	166943771896 ps
T223	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.1705450471			Aug 28 08:21:04 PM UTC 24	Aug 28 08:23:51 PM UTC 24	178697932019 ps
T257	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.382029136			Aug 28 08:17:28 PM UTC 24	Aug 28 08:24:04 PM UTC 24	403740810947 ps
T216	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2219747612			Aug 28 08:23:52 PM UTC 24	Aug 28 08:24:06 PM UTC 24	15171017219 ps
T409	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.430211959			Aug 28 08:24:07 PM UTC 24	Aug 28 08:24:11 PM UTC 24	510753091 ps
T410	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3097396217			Aug 28 08:14:03 PM UTC 24	Aug 28 08:24:12 PM UTC 24	209264965482 ps
T411	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.4267342449			Aug 28 08:23:29 PM UTC 24	Aug 28 08:24:18 PM UTC 24	30924779673 ps
T412	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.1460730833			Aug 28 08:24:12 PM UTC 24	Aug 28 08:24:38 PM UTC 24	5845964737 ps
T413	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.3379519410			Aug 28 08:22:03 PM UTC 24	Aug 28 08:24:40 PM UTC 24	37663190788 ps
T57	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2847737994			Aug 28 08:16:33 PM UTC 24	Aug 28 08:24:53 PM UTC 24	85042681049 ps
T59	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.3300648722			Aug 28 08:12:59 PM UTC 24	Aug 28 08:25:13 PM UTC 24	99453738075 ps
T414	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.4080295212			Aug 28 08:21:22 PM UTC 24	Aug 28 08:25:14 PM UTC 24	490210134800 ps
T152	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.2916268109			Aug 28 08:23:24 PM UTC 24	Aug 28 08:25:18 PM UTC 24	337186309775 ps
T415	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.2371634700			Aug 28 08:20:11 PM UTC 24	Aug 28 08:25:22 PM UTC 24	494077778323 ps
T416	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.2983989200			Aug 28 08:25:23 PM UTC 24	Aug 28 08:25:38 PM UTC 24	2991447829 ps
T153	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.1724010478			Aug 28 08:16:16 PM UTC 24	Aug 28 08:25:38 PM UTC 24	331975151738 ps
T61	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.2311261589			Aug 28 08:13:40 PM UTC 24	Aug 28 08:25:47 PM UTC 24	77815125793 ps
T225	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3185401622			Aug 28 08:25:15 PM UTC 24	Aug 28 08:25:50 PM UTC 24	158799936168 ps
T417	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.1901976879			Aug 28 08:25:40 PM UTC 24	Aug 28 08:25:51 PM UTC 24	37883473653 ps
T418	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.3588178718			Aug 28 08:25:52 PM UTC 24	Aug 28 08:25:55 PM UTC 24	396557639 ps
T29	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1486062163			Aug 28 08:25:48 PM UTC 24	Aug 28 08:25:57 PM UTC 24	1626725210 ps
T419	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.3885823875			Aug 28 08:25:56 PM UTC 24	Aug 28 08:25:59 PM UTC 24	6076351224 ps
T154	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.1131960305			Aug 28 08:12:18 PM UTC 24	Aug 28 08:26:02 PM UTC 24	282090320970 ps
T420	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.4042282362			Aug 28 08:24:41 PM UTC 24	Aug 28 08:26:15 PM UTC 24	161342684303 ps
T233	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.2377243826			Aug 28 08:18:16 PM UTC 24	Aug 28 08:26:27 PM UTC 24	485746169949 ps
T229	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.1068260737			Aug 28 08:18:51 PM UTC 24	Aug 28 08:26:31 PM UTC 24	512305149766 ps
T195	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.277565680			Aug 28 08:22:43 PM UTC 24	Aug 28 08:26:38 PM UTC 24	329326300382 ps
T421	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3752143241			Aug 28 08:23:07 PM UTC 24	Aug 28 08:26:50 PM UTC 24	324893338452 ps
T155	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.1209349444			Aug 28 08:24:05 PM UTC 24	Aug 28 08:26:56 PM UTC 24	349612649812 ps
T422	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.2889082925			Aug 28 08:24:19 PM UTC 24	Aug 28 08:26:58 PM UTC 24	160594556348 ps
T423	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.2419700386			Aug 28 08:26:58 PM UTC 24	Aug 28 08:27:13 PM UTC 24	2973129305 ps
T58	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.1963204071			Aug 28 08:14:17 PM UTC 24	Aug 28 08:27:31 PM UTC 24	288226088775 ps
T282	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.224299465			Aug 28 08:24:13 PM UTC 24	Aug 28 08:27:40 PM UTC 24	165970129614 ps
T30	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.4120618834			Aug 28 08:27:32 PM UTC 24	Aug 28 08:27:42 PM UTC 24	3612674322 ps
T424	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1137978395			Aug 28 08:21:29 PM UTC 24	Aug 28 08:27:44 PM UTC 24	581481862946 ps
T425	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.3814072123			Aug 28 08:27:42 PM UTC 24	Aug 28 08:27:46 PM UTC 24	496539714 ps
T426	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.2487287980			Aug 28 08:27:43 PM UTC 24	Aug 28 08:27:47 PM UTC 24	5998899366 ps
T228	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.1657991086			Aug 28 08:16:50 PM UTC 24	Aug 28 08:28:04 PM UTC 24	209950493688 ps
T373	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.840006700			Aug 28 08:17:50 PM UTC 24	Aug 28 08:28:06 PM UTC 24	111816227873 ps
T240	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.3959534631			Aug 28 08:25:18 PM UTC 24	Aug 28 08:28:09 PM UTC 24	164307732968 ps
T231	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.3449222643			Aug 28 08:14:41 PM UTC 24	Aug 28 08:28:09 PM UTC 24	496050912969 ps
T427	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.1177457846			Aug 28 08:26:59 PM UTC 24	Aug 28 08:28:15 PM UTC 24	34730973167 ps
T428	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3885392010			Aug 28 08:13:15 PM UTC 24	Aug 28 08:28:24 PM UTC 24	484953597516 ps
T235	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.1553086815			Aug 28 08:17:14 PM UTC 24	Aug 28 08:28:25 PM UTC 24	161017941602 ps
T429	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.3090601382			Aug 28 08:28:25 PM UTC 24	Aug 28 08:28:29 PM UTC 24	3344026257 ps
T430	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.1423132694			Aug 28 08:28:26 PM UTC 24	Aug 28 08:28:39 PM UTC 24	31531226191 ps
T377	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.2795864089			Aug 28 08:15:16 PM UTC 24	Aug 28 08:28:49 PM UTC 24	121069514163 ps
T251	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.2434662876			Aug 28 08:23:09 PM UTC 24	Aug 28 08:28:50 PM UTC 24	173111224594 ps
T274	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.4081190971			Aug 28 08:28:39 PM UTC 24	Aug 28 08:28:51 PM UTC 24	2509257346 ps
T431	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.3604653724			Aug 28 08:28:51 PM UTC 24	Aug 28 08:28:53 PM UTC 24	386666727 ps
T432	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.395901525			Aug 28 08:28:52 PM UTC 24	Aug 28 08:29:19 PM UTC 24	6067065123 ps
T388	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.3807521859			Aug 28 08:14:12 PM UTC 24	Aug 28 08:29:35 PM UTC 24	105493997914 ps
T433	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1376369175			Aug 28 08:18:42 PM UTC 24	Aug 28 08:29:37 PM UTC 24	205361374863 ps
T226	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.1506708226			Aug 28 08:20:30 PM UTC 24	Aug 28 08:29:47 PM UTC 24	163127146393 ps
T434	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2199790541			Aug 28 08:26:15 PM UTC 24	Aug 28 08:29:52 PM UTC 24	163669987493 ps
T256	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.350959213			Aug 28 08:20:25 PM UTC 24	Aug 28 08:30:03 PM UTC 24	204826495655 ps
T435	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.133917281			Aug 28 08:26:00 PM UTC 24	Aug 28 08:30:06 PM UTC 24	336064562613 ps
T234	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.3216030578			Aug 28 08:12:48 PM UTC 24	Aug 28 08:30:11 PM UTC 24	321740454748 ps
T436	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.3170601345			Aug 28 08:30:12 PM UTC 24	Aug 28 08:30:18 PM UTC 24	3234880466 ps
T165	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.325440475			Aug 28 08:14:28 PM UTC 24	Aug 28 08:30:25 PM UTC 24	332232548357 ps
T375	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.1759991229			Aug 28 08:23:34 PM UTC 24	Aug 28 08:30:30 PM UTC 24	76706615946 ps
T175	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.274947651			Aug 28 08:28:54 PM UTC 24	Aug 28 08:30:34 PM UTC 24	325567037956 ps
T245	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1340738491			Aug 28 08:30:31 PM UTC 24	Aug 28 08:30:38 PM UTC 24	2607852594 ps
T437	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.4091962162			Aug 28 08:30:19 PM UTC 24	Aug 28 08:30:41 PM UTC 24	41231595391 ps
T438	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.665714543			Aug 28 08:30:39 PM UTC 24	Aug 28 08:30:42 PM UTC 24	418543842 ps
T439	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.3057593746			Aug 28 08:30:41 PM UTC 24	Aug 28 08:30:56 PM UTC 24	5871637102 ps
T239	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.1435705340			Aug 28 08:17:43 PM UTC 24	Aug 28 08:31:31 PM UTC 24	352103202058 ps
T440	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.4085981035			Aug 28 08:16:11 PM UTC 24	Aug 28 08:31:35 PM UTC 24	392088846888 ps
T253	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.1052365148			Aug 28 08:17:23 PM UTC 24	Aug 28 08:32:04 PM UTC 24	354965151499 ps
T227	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.132362228			Aug 28 08:21:55 PM UTC 24	Aug 28 08:32:14 PM UTC 24	196724449358 ps
T250	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.4112496449			Aug 28 08:12:36 PM UTC 24	Aug 28 08:33:19 PM UTC 24	493996725697 ps
T232	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.1002052933			Aug 28 08:28:11 PM UTC 24	Aug 28 08:33:34 PM UTC 24	594366225550 ps
T287	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.4291553929			Aug 28 08:27:44 PM UTC 24	Aug 28 08:33:41 PM UTC 24	160914719187 ps
T441	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.347723545			Aug 28 08:33:42 PM UTC 24	Aug 28 08:33:50 PM UTC 24	5373951892 ps
T379	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.3198025972			Aug 28 08:25:40 PM UTC 24	Aug 28 08:33:57 PM UTC 24	105122499164 ps
T224	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.3553418896			Aug 28 08:28:16 PM UTC 24	Aug 28 08:34:01 PM UTC 24	334733767198 ps
T442	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.1195961786			Aug 28 08:33:51 PM UTC 24	Aug 28 08:34:04 PM UTC 24	36885013254 ps
T443	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3928132886			Aug 28 08:28:10 PM UTC 24	Aug 28 08:34:04 PM UTC 24	600429399191 ps
T444	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.3602900250			Aug 28 08:34:05 PM UTC 24	Aug 28 08:34:08 PM UTC 24	410810687 ps
T445	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.1518324537			Aug 28 08:13:47 PM UTC 24	Aug 28 08:34:14 PM UTC 24	492996575998 ps
T446	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.3573794879			Aug 28 08:34:09 PM UTC 24	Aug 28 08:34:17 PM UTC 24	5952435735 ps
T254	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.290228815			Aug 28 08:34:02 PM UTC 24	Aug 28 08:34:22 PM UTC 24	20005321704 ps
T447	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.3175190778			Aug 28 08:29:20 PM UTC 24	Aug 28 08:34:31 PM UTC 24	320697272625 ps
T380	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.909331462			Aug 28 08:19:15 PM UTC 24	Aug 28 08:34:31 PM UTC 24	122445824364 ps
T448	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1388840391			Aug 28 08:32:14 PM UTC 24	Aug 28 08:34:39 PM UTC 24	199480098884 ps
T267	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.2979016805			Aug 28 08:18:46 PM UTC 24	Aug 28 08:34:45 PM UTC 24	329070781480 ps
T258	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.2324605571			Aug 28 08:28:06 PM UTC 24	Aug 28 08:34:55 PM UTC 24	169807777472 ps
T236	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.3556648386			Aug 28 08:12:47 PM UTC 24	Aug 28 08:35:00 PM UTC 24	645364121706 ps
T449	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.3678008205			Aug 28 08:35:01 PM UTC 24	Aug 28 08:35:06 PM UTC 24	5440513135 ps
T374	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.2082356345			Aug 28 08:28:30 PM UTC 24	Aug 28 08:35:14 PM UTC 24	76173669956 ps
T176	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.2761377451			Aug 28 08:29:48 PM UTC 24	Aug 28 08:35:22 PM UTC 24	628089875578 ps
T310	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.908678921			Aug 28 08:29:36 PM UTC 24	Aug 28 08:35:24 PM UTC 24	167647827832 ps
T450	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.2056102290			Aug 28 08:35:24 PM UTC 24	Aug 28 08:35:26 PM UTC 24	375593451 ps
T190	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.813884970			Aug 28 08:34:22 PM UTC 24	Aug 28 08:35:34 PM UTC 24	328536173385 ps
T241	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.562452818			Aug 28 08:25:51 PM UTC 24	Aug 28 08:35:43 PM UTC 24	352021327655 ps
T451	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2403321145			Aug 28 08:25:14 PM UTC 24	Aug 28 08:35:44 PM UTC 24	391152327196 ps
T452	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.3852412114			Aug 28 08:35:27 PM UTC 24	Aug 28 08:35:45 PM UTC 24	5496043885 ps
T238	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.4227129939			Aug 28 08:35:14 PM UTC 24	Aug 28 08:36:02 PM UTC 24	86055574648 ps
T453	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3576517084			Aug 28 08:23:09 PM UTC 24	Aug 28 08:36:05 PM UTC 24	609111031704 ps
T166	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.2967525396			Aug 28 08:13:35 PM UTC 24	Aug 28 08:36:11 PM UTC 24	513974766554 ps
T454	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1177403349			Aug 28 08:34:31 PM UTC 24	Aug 28 08:36:25 PM UTC 24	164354297015 ps
T455	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.1635358545			Aug 28 08:30:57 PM UTC 24	Aug 28 08:36:27 PM UTC 24	328442647044 ps
T456	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.1370266051			Aug 28 08:36:28 PM UTC 24	Aug 28 08:36:37 PM UTC 24	3756486387 ps
T378	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.1549728811			Aug 28 08:22:08 PM UTC 24	Aug 28 08:36:44 PM UTC 24	126570994027 ps
T457	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.1668140957			Aug 28 08:36:38 PM UTC 24	Aug 28 08:37:09 PM UTC 24	29979349557 ps
T458	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.1864898180			Aug 28 08:20:50 PM UTC 24	Aug 28 08:37:10 PM UTC 24	130042276366 ps
T249	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.3189358946			Aug 28 08:31:32 PM UTC 24	Aug 28 08:37:15 PM UTC 24	490942662977 ps
T246	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.438928991			Aug 28 08:15:24 PM UTC 24	Aug 28 08:37:16 PM UTC 24	642507384924 ps
T31	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3333363870			Aug 28 08:37:10 PM UTC 24	Aug 28 08:37:19 PM UTC 24	6409790163 ps
T459	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.1508534948			Aug 28 08:37:16 PM UTC 24	Aug 28 08:37:20 PM UTC 24	371795202 ps
T329	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.911057519			Aug 28 08:32:05 PM UTC 24	Aug 28 08:37:21 PM UTC 24	176138309945 ps
T255	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.352085343			Aug 28 08:21:25 PM UTC 24	Aug 28 08:37:27 PM UTC 24	389395303672 ps
T460	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.1368239123			Aug 28 08:37:16 PM UTC 24	Aug 28 08:37:31 PM UTC 24	5993440994 ps
T461	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.1172729456			Aug 28 08:35:04 PM UTC 24	Aug 28 08:37:38 PM UTC 24	41031720678 ps
T462	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1687687889			Aug 28 08:20:25 PM UTC 24	Aug 28 08:37:40 PM UTC 24	401374996413 ps
T463	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.3430696280			Aug 28 08:38:16 PM UTC 24	Aug 28 08:38:32 PM UTC 24	5935686257 ps
T275	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.1072977887			Aug 28 08:30:42 PM UTC 24	Aug 28 08:37:48 PM UTC 24	161648527410 ps
T464	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.3029147309			Aug 28 08:30:26 PM UTC 24	Aug 28 08:37:51 PM UTC 24	74723339662 ps
T196	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled.194571936			Aug 28 08:35:35 PM UTC 24	Aug 28 08:38:02 PM UTC 24	165892810699 ps
T465	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.3405073631			Aug 28 08:37:52 PM UTC 24	Aug 28 08:38:06 PM UTC 24	5229622159 ps
T247	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.371266774			Aug 28 08:14:07 PM UTC 24	Aug 28 08:38:10 PM UTC 24	507928517421 ps
T466	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.4195650166			Aug 28 08:22:50 PM UTC 24	Aug 28 08:38:12 PM UTC 24	317938839957 ps
T467	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled_fixed.2956668353			Aug 28 08:37:21 PM UTC 24	Aug 28 08:38:13 PM UTC 24	166833254675 ps
T32	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2478307724			Aug 28 08:38:11 PM UTC 24	Aug 28 08:38:16 PM UTC 24	617099386 ps
T468	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.2808020517			Aug 28 08:38:13 PM UTC 24	Aug 28 08:38:17 PM UTC 24	344748478 ps
T197	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled.2792347089			Aug 28 08:34:15 PM UTC 24	Aug 28 08:38:17 PM UTC 24	322461932411 ps
T264	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.2947863945			Aug 28 08:20:14 PM UTC 24	Aug 28 08:38:54 PM UTC 24	494528287186 ps
T237	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.385475463			Aug 28 08:34:05 PM UTC 24	Aug 28 08:38:54 PM UTC 24	529547178002 ps
T244	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.2275135904			Aug 28 08:13:41 PM UTC 24	Aug 28 08:38:57 PM UTC 24	328071291740 ps
T270	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.4270390387			Aug 28 08:16:11 PM UTC 24	Aug 28 08:39:00 PM UTC 24	523368381763 ps
T230	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_both.949590895			Aug 28 08:37:49 PM UTC 24	Aug 28 08:39:16 PM UTC 24	162230380843 ps
T321	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.313542026			Aug 28 08:21:21 PM UTC 24	Aug 28 08:39:16 PM UTC 24	329074671480 ps
T261	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.1463098671			Aug 28 08:24:39 PM UTC 24	Aug 28 08:39:21 PM UTC 24	332712804174 ps
T469	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_poweron_counter.3694348451			Aug 28 08:39:17 PM UTC 24	Aug 28 08:39:23 PM UTC 24	4031668202 ps
T305	/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.877891769			Aug 28 08:27:41 PM UTC 24	Aug 28 08:39:35 PM UTC 24	453617980701 ps