Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23659

1

T2

20

T3

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20335

1

T2

20

T3

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3324

1

T8

9

T15

8

T17

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17873

1

T2

20

T3

1

T4

13

auto[1]

5786

1

T3

2

T12

24

T16

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19765

1

T2

20

T3

2

T4

13

auto[1]

3894

1

T3

1

T8

3

T12

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T107	14		T217	6		-	-
values[0]	25	1			T218	1		T219	24		-	-
values[1]	580	1			T8	9		T20	7		T47	1
values[2]	848	1			T3	2		T13	8		T14	6
values[3]	565	1			T17	1		T47	1		T156	4
values[4]	874	1			T19	7		T49	4		T139	13
values[5]	2880	1			T12	24		T15	8		T81	1
values[6]	692	1			T18	4		T52	14		T53	15
values[7]	664	1			T53	16		T163	1		T137	27
values[8]	750	1			T151	1		T157	17		T138	31
values[9]	1083	1			T19	9		T158	1		T136	15
minimum	14678	1			T2	20		T3	1		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1007	1			T3	2		T8	9		T14	6
values[1]	492	1			T13	8		T47	1		T54	1
values[2]	842	1			T17	1		T49	4		T142	1
values[3]	2999	1			T12	24		T19	7		T81	1
values[4]	659	1			T15	8		T52	14		T137	2
values[5]	654	1			T18	4		T53	31		T150	1
values[6]	654	1			T163	1		T137	27		T220	1
values[7]	683	1			T151	1		T157	17		T51	2
values[8]	824	1			T19	9		T206	12		T140	16
values[9]	167	1			T158	1		T136	15		T152	27
minimum	14678	1			T2	20		T3	1		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

4203

1

T8

3

T13

4

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T3	2		T14	5		T16	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T8	6		T20	5		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	5		T47	1		T139	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T54	1		T221	3		T50	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T49	4		T142	1		T152	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T17	1		T222	1		T144	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1654	1			T12	3		T19	1		T81	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T156	1		T223	17		T224	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T225	9		T226	20		T227	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T15	8		T52	14		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T53	11		T164	13		T138	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T18	3		T150	1		T155	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T220	1		T28	4		T228	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T163	1		T137	9		T229	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T151	1		T138	18		T56	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T157	1		T51	2		T56	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T19	1		T206	12		T216	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T140	1		T222	2		T58	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T158	1		T195	1		T230	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T136	15		T152	16		T231	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14582	1			T2	20		T4	13		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T14	1		T16	11		T188	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	3		T20	2		T156	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T13	3		T232	10		T191	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T221	2		T50	1		T190	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T152	6		T233	10		T234	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T235	8		T236	9		T237	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T12	21		T19	6		T141	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T156	3		T223	16		T224	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T225	7		T226	13		T227	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T137	1		T138	1		T238	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T53	20		T164	13		T138	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T18	1		T155	9		T171	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T28	2		T228	9		T224	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T137	18		T229	12		T239	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T138	13		T56	8		T174	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T157	16		T56	10		T220	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T19	8		T216	1		T240	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T140	15		T234	13		T241	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T230	9		T242	8		T243	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T152	11		T231	13		T244	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	1		T40	1		T216	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T217	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T107	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T218	1		T219	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T48	1		T153	12		T229	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	6		T20	5		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T3	2		T13	5		T14	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T137	8		T208	1		T146	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T47	1		T139	13		T233	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T17	1		T156	1		T54	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T19	1		T49	4		T139	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T138	1		T222	1		T235	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1610	1			T12	3		T81	1		T141	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T15	8		T137	1		T223	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T53	10		T164	13		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T18	3		T52	14		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T53	1		T138	15		T28	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T163	1		T137	9		T153	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T151	1		T138	18		T56	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T157	1		T56	12		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T19	1		T158	1		T206	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T136	15		T140	1		T51	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14582	1			T2	20		T4	13		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T217	5		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T107	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T219	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T153	11		T229	10		T232	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	3		T20	2		T156	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	3		T14	1		T16	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T137	6		T146	9		T245	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T233	10		T246	15		T247	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T156	3		T221	2		T50	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T19	6		T152	6		T155	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T138	1		T235	8		T224	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	951	1			T12	21		T141	14		T248	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T137	1		T223	16		T249	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T53	5		T164	13		T250	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T18	1		T238	2		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T53	15		T138	15		T28	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T137	18		T153	11		T155	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T138	13		T56	8		T233	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T157	16		T56	10		T220	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T19	8		T174	12		T216	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T140	15		T152	11		T231	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	1		T40	1		T216	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T3	2		T14	5		T16	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T8	6		T20	5		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T13	4		T47	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T54	1		T221	3		T50	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T49	3		T142	1		T152	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T17	1		T222	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T12	24		T19	7		T81	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T156	4		T223	17		T224	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T225	8		T226	14		T227	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T15	1		T52	1		T137	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T53	22		T164	14		T138	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T18	3		T150	1		T155	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T220	1		T28	5		T228	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T163	1		T137	19		T229	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T151	1		T138	14		T56	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T157	17		T51	2		T56	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T19	9		T206	1		T216	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T140	16		T222	2		T58	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T158	1		T195	1		T230	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T136	1		T152	12		T231	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14678	1			T2	20		T3	1		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T14	1		T188	8		T153	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T8	3		T20	2		T137	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	4		T139	12		T232	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T221	2		T50	1		T136	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T49	1		T152	6		T154	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T144	13		T251	7		T236	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T135	33		T139	12		T252	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T223	16		T224	2		T236	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T225	8		T226	19		T227	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T15	7		T52	13		T238	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T53	9		T164	12		T138	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T18	1		T155	9		T171	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T28	1		T228	6		T253	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T137	8		T229	13		T241	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T138	17		T56	10		T174	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T56	11		T153	11		T237	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T206	11		T240	4		T254	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T234	13		T255	26		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T242	9		T243	1		T192	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T136	14		T152	15		T107	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T217	6		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T107	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T218	1		T219	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T48	1		T153	12		T229	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T8	6		T20	5		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	2		T13	4		T14	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T137	7		T208	1		T146	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T47	1		T139	1		T233	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T17	1		T156	4		T54	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T19	7		T49	3		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T138	2		T222	1		T235	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T12	24		T81	1		T141	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	1		T137	2		T223	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T53	6		T164	14		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T18	3		T52	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T53	16		T138	16		T28	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T163	1		T137	19		T153	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T151	1		T138	14		T56	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T157	17		T56	11		T220	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T19	9		T158	1		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T136	1		T140	16		T51	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14678	1			T2	20		T3	1		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T107	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T219	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T153	11		T229	7		T256	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T8	3		T20	2		T166	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T13	4		T14	1		T188	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T137	7		T146	11		T245	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T139	12		T246	2		T247	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T221	2		T50	1		T136	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T49	1		T139	12		T152	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T224	2		T236	5		T247	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T135	33		T252	27		T257	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T15	7		T223	16		T246	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T53	9		T164	12		T253	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T18	1		T52	13		T238	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T138	14		T28	1		T189	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T137	8		T153	11		T155	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T138	17		T56	10		T229	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T56	11		T229	13		T237	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T206	11		T174	10		T240	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T136	14		T152	15		T234	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

auto[0]

4203

1

T8

3

T13

4

T14

1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23659

1

T2

20

T3

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20283

1

T2

20

T3

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3376

1

T8

9

T15

8

T17

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18001

1

T2

20

T3

1

T4

13

auto[1]

5658

1

T3

2

T12

24

T16

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19765

1

T2

20

T3

2

T4

13

auto[1]

3894

1

T3

1

T8

3

T12

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	238	1			T158	1		T222	2		T152	27
values[1]	627	1			T8	9		T20	7		T47	1
values[2]	738	1			T3	2		T13	8		T14	6
values[3]	641	1			T17	1		T47	1		T54	1
values[4]	932	1			T19	7		T156	4		T49	4
values[5]	2710	1			T12	24		T15	8		T81	1
values[6]	808	1			T18	4		T52	14		T53	15
values[7]	691	1			T53	16		T137	27		T138	30
values[8]	713	1			T163	1		T151	1		T157	17
values[9]	883	1			T19	9		T136	15		T206	12
minimum	14678	1			T2	20		T3	1		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	757	1			T3	2		T8	9		T16	12
values[1]	516	1			T13	8		T14	6		T47	1
values[2]	814	1			T17	1		T49	4		T221	5
values[3]	3050	1			T12	24		T19	7		T81	1
values[4]	619	1			T15	8		T52	14		T137	2
values[5]	655	1			T18	4		T53	31		T150	1
values[6]	661	1			T157	17		T137	27		T138	30
values[7]	715	1			T163	1		T151	1		T51	2
values[8]	844	1			T19	9		T158	1		T136	15
values[9]	128	1			T152	27		T195	1		T231	14
minimum	14900	1			T2	20		T3	1		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

4203

1

T8

3

T13

4

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	2		T16	1		T48	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	6		T20	5		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	5		T14	5		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T54	1		T50	4		T136	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T49	4		T154	8		T233	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T17	1		T221	3		T136	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1677	1			T12	3		T19	1		T81	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T156	1		T222	1		T224	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T225	9		T227	19		T258	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T15	8		T52	14		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T53	11		T164	13		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T18	3		T150	1		T155	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T137	9		T138	15		T28	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T157	1		T229	14		T239	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T51	2		T138	18		T56	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T163	1		T151	1		T56	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T19	1		T158	1		T206	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T136	15		T140	1		T222	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T195	1		T242	10		T192	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T152	16		T231	1		T244	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14653	1			T2	20		T4	13		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T47	1		T156	1		T166	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T16	11		T249	18		T259	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	3		T20	2		T137	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T13	3		T14	1		T188	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T50	1		T190	13		T107	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T233	10		T235	8		T234	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T221	2		T237	6		T178	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T12	21		T19	6		T141	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T156	3		T224	12		T236	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T225	7		T227	1		T166	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T137	1		T138	1		T238	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T53	20		T164	13		T189	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T18	1		T155	9		T260	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T137	18		T138	15		T28	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T157	16		T229	12		T239	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T138	13		T56	8		T174	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T56	10		T220	7		T237	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T19	8		T216	1		T240	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T140	15		T231	2		T234	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T242	8		T217	5		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T152	11		T231	13		T244	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	1		T40	1		T216	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T156	10		T166	12		T261	14