Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23659

1

T2

20

T3

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19950

1

T2

20

T3

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3709

1

T8

9

T13

8

T15

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17565

1

T2

20

T3

1

T4

13

auto[1]

6094

1

T3

2

T12

24

T13

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19765

1

T2

20

T3

2

T4

13

auto[1]

3894

1

T3

1

T8

3

T12

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	227	1			T3	2		T18	4		T157	17
values[0]	29	1			T262	14		T291	1		T341	14
values[1]	731	1			T136	15		T206	12		T139	13
values[2]	798	1			T8	9		T13	8		T221	5
values[3]	520	1			T16	12		T158	1		T138	31
values[4]	563	1			T14	6		T15	8		T47	1
values[5]	675	1			T156	11		T137	2		T146	21
values[6]	759	1			T19	7		T20	7		T53	16
values[7]	788	1			T19	9		T150	1		T156	4
values[8]	552	1			T17	1		T47	1		T48	1
values[9]	3339	1			T12	24		T52	14		T53	15
minimum	14678	1			T2	20		T3	1		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	776	1			T136	15		T206	12		T139	13
values[1]	664	1			T8	9		T13	8		T16	12
values[2]	523	1			T14	6		T50	5		T138	31
values[3]	676	1			T15	8		T47	1		T156	11
values[4]	616	1			T137	2		T222	1		T146	21
values[5]	793	1			T19	16		T20	7		T53	16
values[6]	2978	1			T12	24		T17	1		T81	1
values[7]	652	1			T47	1		T52	14		T229	26
values[8]	923	1			T150	1		T54	1		T157	17
values[9]	140	1			T3	2		T18	4		T53	15
minimum	14918	1			T2	20		T3	1		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

4203

1

T8

3

T13

4

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T139	13		T220	1		T233	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T136	15		T206	12		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T16	1		T221	3		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T8	6		T13	5		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T14	5		T138	18		T152	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T50	4		T153	12		T250	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T47	1		T56	12		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T15	8		T156	1		T49	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T222	1		T153	12		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T137	1		T146	12		T28	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T19	1		T53	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T19	1		T20	5		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1675	1			T12	3		T81	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T17	1		T156	1		T136	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T155	19		T232	3		T70	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T47	1		T52	14		T229	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T150	1		T54	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T164	13		T188	9		T223	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T3	2		T242	10		T326	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T18	3		T53	10		T330	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14630	1			T2	20		T4	13		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T266	9		T262	8		T281	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T220	7		T233	2		T232	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T140	15		T239	13		T236	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T16	11		T221	2		T137	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	3		T13	3		T174	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	1		T138	13		T152	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T50	1		T153	11		T250	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T56	10		T216	1		T234	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T156	10		T238	2		T292	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T153	11		T231	6		T250	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T137	1		T146	9		T28	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T19	6		T53	15		T137	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T19	8		T20	2		T138	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T12	21		T141	14		T248	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T156	3		T228	9		T240	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T155	13		T232	2		T333	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T229	12		T224	12		T236	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T157	16		T138	15		T56	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T164	13		T188	2		T223	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T242	8		T322	12		T342	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T18	1		T53	5		T330	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T3	1		T40	1		T216	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T266	8		T262	6		T343	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T3	2		T157	1		T208	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T18	3		T282	1		T267	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T291	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T262	8		T341	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T139	13		T220	1		T233	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T136	15		T206	12		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T221	3		T137	8		T189	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	6		T13	5		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T16	1		T158	1		T138	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T153	12		T250	1		T310	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T14	5		T47	1		T56	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T15	8		T49	4		T50	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T231	1		T245	2		T250	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T156	1		T137	1		T146	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T19	1		T53	1		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T20	5		T163	1		T51	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T150	1		T151	1		T136	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T19	1		T156	1		T136	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T48	1		T155	19		T244	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T17	1		T47	1		T233	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1742	1			T12	3		T81	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T52	14		T53	10		T164	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14582	1			T2	20		T4	13		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T157	16		T56	8		T249	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T18	1		T267	10		T317	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T262	6		T341	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T220	7		T233	2		T232	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T140	15		T237	13		T266	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T221	2		T137	6		T189	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T8	3		T13	3		T174	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T16	11		T138	13		T234	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T153	11		T250	13		T310	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T14	1		T56	10		T216	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T50	1		T246	7		T264	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T231	6		T245	1		T250	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T156	10		T137	1		T146	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T19	6		T53	15		T153	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T20	2		T138	1		T28	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T137	18		T225	7		T166	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T19	8		T156	3		T228	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T155	13		T244	8		T200	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T233	11		T229	12		T236	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T12	21		T141	14		T248	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T53	5		T164	13		T188	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	1		T40	1		T216	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T139	1		T220	8		T233	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T136	1		T206	1		T140	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T16	12		T221	3		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T8	6		T13	4		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	5		T138	14		T152	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T50	4		T153	12		T250	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T47	1		T56	11		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T15	1		T156	11		T49	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T222	1		T153	12		T231	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T137	2		T146	10		T28	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T19	7		T53	16		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T19	9		T20	5		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T12	24		T81	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T17	1		T156	4		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T155	14		T232	3		T70	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T47	1		T52	1		T229	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T150	1		T54	1		T157	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T164	14		T188	3		T223	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T3	2		T242	9		T326	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T18	3		T53	6		T330	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14700	1			T2	20		T3	1		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T266	9		T262	7		T281	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T139	12		T247	6		T280	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T136	14		T206	11		T236	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T221	2		T137	7		T189	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	3		T13	4		T174	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T14	1		T138	17		T152	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T50	1		T153	11		T246	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T56	11		T154	7		T234	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T15	7		T49	1		T139	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T153	11		T270	19		T344	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T146	11		T28	1		T229	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T137	8		T155	9		T323	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T20	2		T239	10		T253	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T135	33		T136	8		T252	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T136	8		T228	6		T240	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T155	18		T232	2		T333	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T52	13		T229	13		T224	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T138	14		T56	10		T229	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T164	12		T188	8		T223	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T242	9		T326	16		T322	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T18	1		T53	9		T330	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T211	2		T294	4		T344	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T266	8		T262	7		T281	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T3	2		T157	17		T208	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T18	3		T282	1		T267	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T291	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T262	7		T341	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T139	1		T220	8		T233	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T136	1		T206	1		T140	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T221	3		T137	7		T189	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T8	6		T13	4		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T16	12		T158	1		T138	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T153	12		T250	14		T310	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T14	5		T47	1		T56	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T15	1		T49	3		T50	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T231	7		T245	2		T250	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T156	11		T137	2		T146	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T19	7		T53	16		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T20	5		T163	1		T51	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T150	1		T151	1		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T19	9		T156	4		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T48	1		T155	14		T244	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T17	1		T47	1		T233	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T12	24		T81	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T52	1		T53	6		T164	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14678	1			T2	20		T3	1		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T56	10		T176	6		T212	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T18	1		T267	11		T258	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T262	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T139	12		T107	4		T211	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T136	14		T206	11		T237	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T221	2		T137	7		T189	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	3		T13	4		T174	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T138	17		T234	13		T166	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T153	11		T316	7		T334	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	1		T56	11		T152	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T15	7		T49	1		T50	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T245	1		T224	9		T267	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T146	11		T229	7		T253	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T153	11		T155	9		T270	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T20	2		T28	1		T239	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T136	8		T137	8		T225	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T136	8		T228	6		T240	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T155	18		T200	12		T333	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T229	13		T236	5		T105	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T135	33		T138	14		T252	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T52	13		T53	9		T164	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

auto[0]

4203

1

T8

3

T13

4

T14

1