CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 23659 | 1 | T2 | 20 | T3 | 3 | T4 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[ADC_CTRL_FILTER_COND_IN] | 20191 | 1 | T2 | 20 | T3 | 1 | T4 | 13 | ||||
auto[ADC_CTRL_FILTER_COND_OUT] | 3468 | 1 | T3 | 2 | T8 | 9 | T13 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 17519 | 1 | T2 | 20 | T3 | 1 | T4 | 13 | ||||
auto[1] | 6140 | 1 | T3 | 2 | T8 | 9 | T12 | 24 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19765 | 1 | T2 | 20 | T3 | 2 | T4 | 13 | ||||
auto[1] | 3894 | 1 | T3 | 1 | T8 | 3 | T12 | 21 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 0 | 12 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
maximum | 300 | 1 | T19 | 9 | T28 | 6 | T233 | 11 | ||||
values[0] | 54 | 1 | T334 | 9 | T299 | 28 | T218 | 1 | ||||
values[1] | 769 | 1 | T19 | 7 | T150 | 1 | T164 | 26 | ||||
values[2] | 858 | 1 | T157 | 17 | T136 | 9 | T140 | 16 | ||||
values[3] | 558 | 1 | T16 | 12 | T47 | 1 | T163 | 1 | ||||
values[4] | 670 | 1 | T8 | 9 | T15 | 8 | T20 | 7 | ||||
values[5] | 2936 | 1 | T12 | 24 | T53 | 15 | T81 | 1 | ||||
values[6] | 614 | 1 | T13 | 8 | T156 | 4 | T206 | 12 | ||||
values[7] | 635 | 1 | T18 | 4 | T48 | 1 | T54 | 1 | ||||
values[8] | 761 | 1 | T3 | 2 | T14 | 6 | T17 | 1 | ||||
values[9] | 826 | 1 | T47 | 1 | T150 | 1 | T151 | 1 | ||||
minimum | 14678 | 1 | T2 | 20 | T3 | 1 | T4 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 1 | 11 | 91.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
maximum | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 727 | 1 | T164 | 26 | T174 | 23 | T152 | 27 | ||||
values[1] | 863 | 1 | T16 | 12 | T163 | 1 | T157 | 17 | ||||
values[2] | 545 | 1 | T20 | 7 | T47 | 1 | T137 | 27 | ||||
values[3] | 2932 | 1 | T8 | 9 | T12 | 24 | T15 | 8 | ||||
values[4] | 684 | 1 | T53 | 15 | T156 | 4 | T216 | 5 | ||||
values[5] | 558 | 1 | T13 | 8 | T206 | 12 | T208 | 1 | ||||
values[6] | 604 | 1 | T14 | 6 | T18 | 4 | T48 | 1 | ||||
values[7] | 773 | 1 | T3 | 2 | T17 | 1 | T52 | 14 | ||||
values[8] | 835 | 1 | T47 | 1 | T150 | 1 | T151 | 1 | ||||
values[9] | 158 | 1 | T19 | 9 | T137 | 14 | T28 | 6 | ||||
minimum | 14980 | 1 | T2 | 20 | T3 | 1 | T4 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19456 | 1 | T2 | 20 | T3 | 3 | T4 | 13 | ||||
auto[1] | 4203 | 1 | T8 | 3 | T13 | 4 | T14 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 186 | 1 | T229 | 8 | T251 | 8 | T245 | 2 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 206 | 1 | T164 | 13 | T174 | 11 | T152 | 16 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 159 | 1 | T136 | 9 | T189 | 12 | T238 | 7 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 314 | 1 | T16 | 1 | T163 | 1 | T157 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 149 | 1 | T137 | 9 | T233 | 1 | T229 | 14 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 146 | 1 | T20 | 5 | T47 | 1 | T146 | 12 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 1592 | 1 | T12 | 3 | T15 | 8 | T81 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 198 | 1 | T8 | 6 | T139 | 13 | T152 | 7 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 169 | 1 | T156 | 1 | T216 | 4 | T231 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 210 | 1 | T53 | 10 | T154 | 8 | T256 | 20 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 115 | 1 | T208 | 1 | T51 | 2 | T142 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 206 | 1 | T13 | 5 | T206 | 12 | T56 | 12 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 170 | 1 | T14 | 5 | T188 | 9 | T239 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 199 | 1 | T18 | 3 | T48 | 1 | T54 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 228 | 1 | T17 | 1 | T53 | 1 | T156 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 189 | 1 | T3 | 2 | T52 | 14 | T222 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 243 | 1 | T47 | 1 | T151 | 1 | T221 | 3 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 228 | 1 | T150 | 1 | T137 | 1 | T56 | 11 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 71 | 1 | T137 | 8 | T28 | 4 | T274 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 18 | 1 | T19 | 1 | T100 | 1 | T290 | 1 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 14695 | 1 | T2 | 20 | T4 | 13 | T5 | 20 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 74 | 1 | T150 | 1 | T158 | 1 | T144 | 14 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 185 | 1 | T245 | 1 | T247 | 4 | T328 | 10 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 150 | 1 | T164 | 13 | T174 | 12 | T152 | 11 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 84 | 1 | T189 | 4 | T238 | 2 | T249 | 2 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 306 | 1 | T16 | 11 | T157 | 16 | T140 | 15 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 131 | 1 | T137 | 18 | T233 | 11 | T229 | 12 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 119 | 1 | T20 | 2 | T146 | 9 | T233 | 2 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 1004 | 1 | T12 | 21 | T141 | 14 | T248 | 11 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 138 | 1 | T8 | 3 | T152 | 6 | T153 | 11 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 129 | 1 | T156 | 3 | T216 | 1 | T231 | 2 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 176 | 1 | T53 | 5 | T250 | 11 | T166 | 15 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 112 | 1 | T155 | 9 | T231 | 6 | T167 | 16 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 125 | 1 | T13 | 3 | T56 | 10 | T228 | 9 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 130 | 1 | T14 | 1 | T188 | 2 | T239 | 13 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 105 | 1 | T18 | 1 | T50 | 1 | T264 | 8 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 236 | 1 | T53 | 15 | T156 | 10 | T240 | 6 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 120 | 1 | T225 | 7 | T232 | 1 | T237 | 6 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 177 | 1 | T221 | 2 | T138 | 13 | T220 | 7 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 187 | 1 | T137 | 1 | T56 | 8 | T233 | 10 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 48 | 1 | T137 | 6 | T28 | 2 | T290 | 4 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 21 | 1 | T19 | 8 | T100 | 12 | T345 | 1 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 178 | 1 | T3 | 1 | T40 | 1 | T19 | 6 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 33 | 1 | T333 | 9 | T346 | 12 | T277 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 3 | 45 | 93.75 | 3 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [values[0]] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 100 | 1 | T28 | 4 | T274 | 1 | T176 | 12 | ||||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 60 | 1 | T19 | 1 | T233 | 1 | T267 | 5 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 27 | 1 | T334 | 6 | T299 | 19 | T218 | 1 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 2 | 1 | T199 | 1 | T347 | 1 | - | - | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 221 | 1 | T19 | 1 | T229 | 8 | T251 | 8 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 215 | 1 | T150 | 1 | T164 | 13 | T158 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 175 | 1 | T136 | 9 | T238 | 7 | T249 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 315 | 1 | T157 | 1 | T140 | 1 | T138 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 135 | 1 | T189 | 12 | T229 | 14 | T253 | 14 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 162 | 1 | T16 | 1 | T47 | 1 | T163 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 150 | 1 | T15 | 8 | T136 | 9 | T137 | 9 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 194 | 1 | T8 | 6 | T20 | 5 | T139 | 13 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 1559 | 1 | T12 | 3 | T81 | 1 | T141 | 2 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 232 | 1 | T53 | 10 | T152 | 7 | T153 | 12 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 180 | 1 | T156 | 1 | T51 | 2 | T142 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 193 | 1 | T13 | 5 | T206 | 12 | T56 | 12 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 153 | 1 | T208 | 1 | T188 | 9 | T155 | 10 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 222 | 1 | T18 | 3 | T48 | 1 | T54 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 235 | 1 | T14 | 5 | T17 | 1 | T53 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 195 | 1 | T3 | 2 | T52 | 14 | T222 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 260 | 1 | T47 | 1 | T151 | 1 | T221 | 3 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 198 | 1 | T150 | 1 | T137 | 1 | T56 | 11 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 14582 | 1 | T2 | 20 | T4 | 13 | T5 | 20 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 74 | 1 | T28 | 2 | T270 | 4 | T348 | 3 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 66 | 1 | T19 | 8 | T233 | 10 | T267 | 4 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 25 | 1 | T334 | 3 | T299 | 9 | T337 | 13 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 210 | 1 | T19 | 6 | T245 | 1 | T236 | 2 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 123 | 1 | T164 | 13 | T174 | 12 | T153 | 11 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 84 | 1 | T238 | 2 | T249 | 2 | T247 | 4 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 284 | 1 | T157 | 16 | T140 | 15 | T138 | 1 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 86 | 1 | T189 | 4 | T229 | 12 | T338 | 9 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 175 | 1 | T16 | 11 | T231 | 13 | T234 | 2 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 220 | 1 | T137 | 18 | T138 | 15 | T233 | 11 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 106 | 1 | T8 | 3 | T20 | 2 | T146 | 9 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 921 | 1 | T12 | 21 | T141 | 14 | T248 | 11 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 224 | 1 | T53 | 5 | T152 | 6 | T153 | 11 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 139 | 1 | T156 | 3 | T216 | 1 | T236 | 9 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 102 | 1 | T13 | 3 | T56 | 10 | T232 | 2 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 129 | 1 | T188 | 2 | T155 | 9 | T231 | 6 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 131 | 1 | T18 | 1 | T50 | 1 | T228 | 9 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 228 | 1 | T14 | 1 | T53 | 15 | T156 | 10 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 103 | 1 | T225 | 7 | T232 | 1 | T237 | 6 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 202 | 1 | T221 | 2 | T137 | 6 | T138 | 13 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 166 | 1 | T137 | 1 | T56 | 8 | T247 | 13 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 96 | 1 | T3 | 1 | T40 | 1 | T216 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 216 | 1 | T229 | 1 | T251 | 1 | T245 | 2 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 182 | 1 | T164 | 14 | T174 | 13 | T152 | 12 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 115 | 1 | T136 | 1 | T189 | 5 | T238 | 6 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 349 | 1 | T16 | 12 | T163 | 1 | T157 | 17 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 159 | 1 | T137 | 19 | T233 | 12 | T229 | 13 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 153 | 1 | T20 | 5 | T47 | 1 | T146 | 10 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 1319 | 1 | T12 | 24 | T15 | 1 | T81 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 173 | 1 | T8 | 6 | T139 | 1 | T152 | 7 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 159 | 1 | T156 | 4 | T216 | 5 | T231 | 3 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 208 | 1 | T53 | 6 | T154 | 1 | T256 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 138 | 1 | T208 | 1 | T51 | 2 | T142 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 166 | 1 | T13 | 4 | T206 | 1 | T56 | 11 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 157 | 1 | T14 | 5 | T188 | 3 | T239 | 14 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 145 | 1 | T18 | 3 | T48 | 1 | T54 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 282 | 1 | T17 | 1 | T53 | 16 | T156 | 11 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 158 | 1 | T3 | 2 | T52 | 1 | T222 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 223 | 1 | T47 | 1 | T151 | 1 | T221 | 3 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 238 | 1 | T150 | 1 | T137 | 2 | T56 | 9 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 60 | 1 | T137 | 7 | T28 | 5 | T274 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 28 | 1 | T19 | 9 | T100 | 13 | T290 | 1 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 14782 | 1 | T2 | 20 | T3 | 1 | T4 | 13 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 46 | 1 | T150 | 1 | T158 | 1 | T144 | 1 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 155 | 1 | T229 | 7 | T251 | 7 | T245 | 1 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 174 | 1 | T164 | 12 | T174 | 10 | T152 | 15 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 128 | 1 | T136 | 8 | T189 | 11 | T238 | 3 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 271 | 1 | T305 | 1 | T280 | 15 | T260 | 2 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 121 | 1 | T137 | 8 | T229 | 13 | T253 | 13 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 112 | 1 | T20 | 2 | T146 | 11 | T155 | 18 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 1277 | 1 | T15 | 7 | T135 | 33 | T136 | 8 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 163 | 1 | T8 | 3 | T139 | 12 | T152 | 6 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 139 | 1 | T236 | 11 | T166 | 12 | T191 | 20 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 178 | 1 | T53 | 9 | T154 | 7 | T256 | 19 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 89 | 1 | T155 | 9 | T107 | 10 | T191 | 10 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 165 | 1 | T13 | 4 | T206 | 11 | T56 | 11 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 143 | 1 | T14 | 1 | T188 | 8 | T227 | 18 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 159 | 1 | T18 | 1 | T50 | 1 | T246 | 2 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 182 | 1 | T49 | 1 | T136 | 14 | T240 | 4 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 151 | 1 | T52 | 13 | T225 | 8 | T237 | 11 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 197 | 1 | T221 | 2 | T139 | 12 | T138 | 17 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 177 | 1 | T56 | 10 | T267 | 4 | T329 | 7 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 59 | 1 | T137 | 7 | T28 | 1 | T290 | 10 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 11 | 1 | T82 | 1 | T340 | 10 | - | - | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 91 | 1 | T236 | 5 | T268 | 9 | T211 | 2 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 61 | 1 | T144 | 13 | T176 | 6 | T177 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | [minimum] | * | -- | -- | 2 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [values[0]] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 90 | 1 | T28 | 5 | T274 | 1 | T176 | 1 | ||||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 79 | 1 | T19 | 9 | T233 | 11 | T267 | 5 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 33 | 1 | T334 | 8 | T299 | 10 | T218 | 1 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 2 | 1 | T199 | 1 | T347 | 1 | - | - | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 248 | 1 | T19 | 7 | T229 | 1 | T251 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 155 | 1 | T150 | 1 | T164 | 14 | T158 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 116 | 1 | T136 | 1 | T238 | 6 | T249 | 3 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 327 | 1 | T157 | 17 | T140 | 16 | T138 | 2 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 111 | 1 | T189 | 5 | T229 | 13 | T253 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 205 | 1 | T16 | 12 | T47 | 1 | T163 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 247 | 1 | T15 | 1 | T136 | 1 | T137 | 19 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 147 | 1 | T8 | 6 | T20 | 5 | T139 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 1232 | 1 | T12 | 24 | T81 | 1 | T141 | 16 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 260 | 1 | T53 | 6 | T152 | 7 | T153 | 12 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 173 | 1 | T156 | 4 | T51 | 2 | T142 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 138 | 1 | T13 | 4 | T206 | 1 | T56 | 11 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 155 | 1 | T208 | 1 | T188 | 3 | T155 | 10 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 177 | 1 | T18 | 3 | T48 | 1 | T54 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 275 | 1 | T14 | 5 | T17 | 1 | T53 | 16 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 139 | 1 | T3 | 2 | T52 | 1 | T222 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 252 | 1 | T47 | 1 | T151 | 1 | T221 | 3 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 217 | 1 | T150 | 1 | T137 | 2 | T56 | 9 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 14678 | 1 | T2 | 20 | T3 | 1 | T4 | 13 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 84 | 1 | T28 | 1 | T176 | 11 | T270 | 7 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 47 | 1 | T267 | 4 | T171 | 1 | T179 | 10 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 19 | 1 | T334 | 1 | T299 | 18 | - | - | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 183 | 1 | T229 | 7 | T251 | 7 | T245 | 1 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 183 | 1 | T164 | 12 | T144 | 13 | T174 | 10 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 143 | 1 | T136 | 8 | T238 | 3 | T247 | 10 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 272 | 1 | T152 | 15 | T254 | 1 | T241 | 13 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 110 | 1 | T189 | 11 | T229 | 13 | T253 | 13 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 132 | 1 | T234 | 2 | T239 | 10 | T305 | 1 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 123 | 1 | T15 | 7 | T136 | 8 | T137 | 8 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 153 | 1 | T8 | 3 | T20 | 2 | T139 | 12 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 1248 | 1 | T135 | 33 | T252 | 27 | T257 | 17 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 196 | 1 | T53 | 9 | T152 | 6 | T153 | 11 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 146 | 1 | T236 | 11 | T166 | 12 | T107 | 10 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 157 | 1 | T13 | 4 | T206 | 11 | T56 | 11 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 127 | 1 | T188 | 8 | T155 | 9 | T227 | 18 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 176 | 1 | T18 | 1 | T50 | 1 | T228 | 6 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 188 | 1 | T14 | 1 | T49 | 1 | T136 | 14 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 159 | 1 | T52 | 13 | T225 | 8 | T237 | 11 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 210 | 1 | T221 | 2 | T137 | 7 | T139 | 12 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 147 | 1 | T56 | 10 | T329 | 7 | T247 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 4 | 2 | 2 | 50.00 | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [auto[1]] | -- | -- | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | auto[0] | 19456 | 1 | T2 | 20 | T3 | 3 | T4 | 13 | ||||
auto[1] | auto[0] | 4203 | 1 | T8 | 3 | T13 | 4 | T14 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |