Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23659

1

T2

20

T3

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20111

1

T2

20

T3

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3548

1

T8

9

T13

8

T15

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17586

1

T2

20

T3

1

T4

13

auto[1]

6073

1

T3

2

T12

24

T13

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19765

1

T2

20

T3

2

T4

13

auto[1]

3894

1

T3

1

T8

3

T12

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	61	1			T157	17		T282	1		T267	22
values[0]	96	1			T233	3		T288	23		T100	13
values[1]	690	1			T136	15		T206	12		T139	13
values[2]	748	1			T8	9		T13	8		T137	14
values[3]	557	1			T16	12		T221	5		T158	1
values[4]	603	1			T14	6		T15	8		T47	1
values[5]	606	1			T156	11		T137	2		T139	13
values[6]	757	1			T19	7		T20	7		T163	1
values[7]	823	1			T19	9		T53	16		T150	1
values[8]	589	1			T17	1		T47	1		T48	1
values[9]	3451	1			T3	2		T12	24		T18	4
minimum	14678	1			T2	20		T3	1		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1009	1			T136	15		T206	12		T139	13
values[1]	632	1			T8	9		T13	8		T16	12
values[2]	502	1			T14	6		T50	5		T138	31
values[3]	692	1			T15	8		T47	1		T156	11
values[4]	612	1			T137	2		T139	13		T222	1
values[5]	845	1			T19	16		T20	7		T53	16
values[6]	2990	1			T12	24		T17	1		T81	1
values[7]	648	1			T47	1		T52	14		T229	26
values[8]	880	1			T53	15		T150	1		T54	1
values[9]	158	1			T3	2		T18	4		T208	1
minimum	14691	1			T2	20		T3	1		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

4203

1

T8

3

T13

4

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T139	13		T233	1		T232	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T136	15		T206	12		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T16	1		T221	3		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	6		T13	5		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	5		T138	18		T234	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T50	4		T153	12		T250	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T47	1		T49	4		T56	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T15	8		T156	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T222	1		T153	12		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T137	1		T139	13		T146	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T19	1		T53	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T19	1		T20	5		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1713	1			T12	3		T17	1		T81	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T156	1		T136	9		T58	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T232	3		T70	1		T316	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T47	1		T52	14		T229	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T150	1		T54	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T53	10		T164	13		T223	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T3	2		T208	1		T349	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T18	3		T188	9		T282	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14583	1			T2	20		T4	13		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T302	3		T350	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T233	2		T232	1		T247	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T140	15		T239	13		T236	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T16	11		T221	2		T137	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T8	3		T13	3		T174	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T14	1		T138	13		T234	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T50	1		T153	11		T250	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T56	10		T216	1		T152	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T156	10		T234	2		T238	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T153	11		T231	6		T250	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T137	1		T146	9		T28	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T19	6		T53	15		T137	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T19	8		T20	2		T138	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T12	21		T141	14		T248	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T156	3		T228	9		T240	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T232	2		T191	5		T333	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T229	12		T224	12		T190	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T157	16		T138	15		T56	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T53	5		T164	13		T223	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T349	8		T242	8		T351	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T18	1		T188	2		T267	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T3	1		T40	1		T220	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T302	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T157	1		T352	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T282	1		T267	12		T279	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T233	1		T288	10		T100	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T262	8		T353	1		T354	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T139	13		T220	1		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T136	15		T206	12		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T137	8		T189	12		T176	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T8	6		T13	5		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T16	1		T221	3		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T153	12		T250	1		T310	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	5		T47	1		T49	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T15	8		T50	4		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T231	1		T245	2		T250	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T156	1		T137	1		T139	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T19	1		T222	1		T153	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T20	5		T163	1		T51	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T53	1		T150	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T19	1		T156	1		T136	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T17	1		T48	1		T155	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T47	1		T233	1		T229	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1819	1			T3	2		T12	3		T81	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T18	3		T52	14		T53	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14582	1			T2	20		T4	13		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T157	16		T352	10		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T267	10		T279	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T233	2		T288	13		T100	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T262	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T220	7		T232	1		T107	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T140	15		T239	13		T237	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T137	6		T189	4		T247	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T8	3		T13	3		T174	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T16	11		T221	2		T138	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T153	11		T250	13		T310	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T14	1		T56	10		T216	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T50	1		T234	2		T246	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T231	6		T245	1		T250	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T156	10		T137	1		T138	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T19	6		T153	11		T155	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T20	2		T28	2		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T53	15		T137	18		T225	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T19	8		T156	3		T228	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T155	13		T166	15		T211	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T233	11		T229	12		T224	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1098	1			T12	21		T141	14		T248	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T18	1		T53	5		T164	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	1		T40	1		T216	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T139	1		T233	3		T232	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T136	1		T206	1		T140	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T16	12		T221	3		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T8	6		T13	4		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	5		T138	14		T234	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T50	4		T153	12		T250	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T47	1		T49	3		T56	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T15	1		T156	11		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T222	1		T153	12		T231	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T137	2		T139	1		T146	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T19	7		T53	16		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T19	9		T20	5		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T12	24		T17	1		T81	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T156	4		T136	1		T58	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T232	3		T70	1		T316	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T47	1		T52	1		T229	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T150	1		T54	1		T157	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T53	6		T164	14		T223	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T3	2		T208	1		T349	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T18	3		T188	3		T282	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14686	1			T2	20		T3	1		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T302	2		T350	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T139	12		T247	6		T280	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T136	14		T206	11		T236	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T221	2		T137	7		T189	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T8	3		T13	4		T174	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T14	1		T138	17		T234	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T50	1		T153	11		T246	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T49	1		T56	11		T152	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	7		T144	13		T256	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T153	11		T270	19		T344	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T139	12		T146	11		T28	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T136	8		T137	8		T155	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T20	2		T239	10		T253	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T135	33		T252	27		T257	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T136	8		T228	6		T240	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T232	2		T191	3		T333	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T52	13		T229	13		T224	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T138	14		T56	10		T229	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T53	9		T164	12		T223	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T242	9		T351	11		T342	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T18	1		T188	8		T267	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T302	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T157	17		T352	11		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T282	1		T267	11		T279	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T233	3		T288	14		T100	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T262	7		T353	1		T354	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T139	1		T220	8		T232	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T136	1		T206	1		T140	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T137	7		T189	5		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T8	6		T13	4		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T16	12		T221	3		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T153	12		T250	14		T310	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T14	5		T47	1		T49	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T15	1		T50	4		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T231	7		T245	2		T250	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T156	11		T137	2		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T19	7		T222	1		T153	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T20	5		T163	1		T51	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T53	16		T150	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T19	9		T156	4		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T17	1		T48	1		T155	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T47	1		T233	12		T229	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1456	1			T3	2		T12	24		T81	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T18	3		T52	1		T53	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14678	1			T2	20		T3	1		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T267	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T288	9		T325	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T262	7		T354	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T139	12		T107	4		T211	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T136	14		T206	11		T237	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T137	7		T189	11		T176	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	3		T13	4		T174	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T221	2		T138	17		T234	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T153	11		T316	7		T334	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	1		T49	1		T56	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T15	7		T50	1		T144	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T245	1		T224	9		T267	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T139	12		T146	11		T253	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T153	11		T155	9		T246	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T20	2		T28	1		T229	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T136	8		T137	8		T225	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T136	8		T228	6		T240	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T155	18		T166	17		T211	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T229	13		T224	2		T255	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1461	1			T135	33		T138	14		T252	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T18	1		T52	13		T53	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

auto[0]

4203

1

T8

3

T13

4

T14

1