Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23659

1

T2

20

T3

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20249

1

T2

20

T3

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3410

1

T13

8

T14

6

T15

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17366

1

T2

20

T3

3

T4

13

auto[1]

6293

1

T12

24

T15

8

T16

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19765

1

T2

20

T3

2

T4

13

auto[1]

3894

1

T3

1

T8

3

T12

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	318	1			T138	31		T144	14		T154	8
values[0]	43	1			T48	1		T169	1		T263	17
values[1]	523	1			T13	8		T14	6		T188	11
values[2]	524	1			T3	2		T19	7		T47	1
values[3]	749	1			T54	1		T206	12		T137	29
values[4]	3038	1			T12	24		T15	8		T17	1
values[5]	597	1			T8	9		T53	16		T150	1
values[6]	736	1			T20	7		T52	14		T164	26
values[7]	700	1			T16	12		T47	1		T156	4
values[8]	730	1			T18	4		T163	1		T156	11
values[9]	1023	1			T19	9		T150	1		T158	1
minimum	14678	1			T2	20		T3	1		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	482	1			T3	2		T14	6		T19	7
values[1]	647	1			T54	1		T157	17		T137	27
values[2]	703	1			T206	12		T137	16		T139	13
values[3]	3017	1			T8	9		T12	24		T15	8
values[4]	560	1			T53	16		T56	22		T174	24
values[5]	930	1			T20	7		T52	14		T156	4
values[6]	509	1			T16	12		T47	1		T163	1
values[7]	790	1			T18	4		T19	9		T156	11
values[8]	896	1			T150	1		T144	14		T220	8
values[9]	249	1			T138	31		T234	27		T190	12
minimum	14876	1			T2	20		T3	1		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

4203

1

T8

3

T13

4

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	2		T195	1		T240	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	5		T19	1		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T157	1		T137	9		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T54	1		T208	1		T233	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T137	9		T139	13		T223	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T206	12		T222	1		T235	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1637	1			T8	6		T12	3		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T15	8		T151	1		T136	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T174	1		T233	1		T274	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T53	1		T56	12		T174	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T138	15		T189	12		T155	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T20	5		T52	14		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T16	1		T163	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T47	1		T136	15		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T18	3		T19	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T139	13		T142	1		T254	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T150	1		T28	4		T153	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T144	14		T220	1		T152	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T138	18		T234	14		T280	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T190	1		T247	7		T283	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14653	1			T2	20		T4	13		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T13	5		T265	3		T306	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T240	6		T227	1		T200	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T14	1		T19	6		T188	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T157	16		T137	18		T152	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T233	11		T229	10		T250	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T137	7		T223	16		T229	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T235	8		T250	13		T236	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T8	3		T12	21		T53	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T138	1		T56	8		T216	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T233	10		T305	3		T355	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T53	15		T56	10		T174	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T138	15		T189	4		T155	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T20	2		T156	3		T164	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T16	11		T140	15		T231	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T153	11		T233	2		T241	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T18	1		T19	8		T156	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T254	1		T238	2		T246	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T28	2		T153	11		T231	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T220	7		T152	11		T225	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T138	13		T234	13		T170	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T190	11		T247	11		T356	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T40	1		T216	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T13	3		T265	11		T306	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T138	18		T154	8		T280	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T144	14		T329	8		T283	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T169	1		T263	1		T92	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T48	1		T35	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T195	1		T240	5		T165	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	5		T14	5		T188	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T3	2		T157	1		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T19	1		T47	1		T233	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T137	10		T139	13		T223	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T54	1		T206	12		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1609	1			T12	3		T17	1		T53	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T15	8		T151	1		T136	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	6		T150	1		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T53	1		T138	1		T56	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T138	15		T189	12		T155	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T20	5		T52	14		T164	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T16	1		T140	1		T51	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T47	1		T156	1		T221	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T18	3		T163	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T139	13		T142	1		T254	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T19	1		T150	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T220	1		T152	16		T225	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14582	1			T2	20		T4	13		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T138	13		T107	2		T170	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T317	9		T311	1		T357	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T263	16		T92	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T35	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T240	6		T227	1		T166	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T13	3		T14	1		T188	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T157	16		T226	13		T268	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T19	6		T233	11		T229	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T137	19		T223	16		T152	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T235	8		T250	24		T236	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T12	21		T53	5		T141	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T56	8		T174	12		T216	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T8	3		T233	10		T270	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T53	15		T138	1		T56	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T138	15		T189	4		T155	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T20	2		T164	13		T245	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T16	11		T140	15		T231	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T156	3		T221	2		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T18	1		T156	10		T234	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T254	1		T241	9		T249	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T19	8		T28	2		T153	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T220	7		T152	11		T225	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	1		T40	1		T216	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T3	2		T195	1		T240	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	5		T19	7		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T157	17		T137	19		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T54	1		T208	1		T233	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T137	9		T139	1		T223	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T206	1		T222	1		T235	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T8	6		T12	24		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T15	1		T151	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T174	1		T233	11		T274	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T53	16		T56	11		T174	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T138	16		T189	5		T155	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T20	5		T52	1		T156	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T16	12		T163	1		T140	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T47	1		T136	1		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T18	3		T19	9		T156	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T139	1		T142	1		T254	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T150	1		T28	5		T153	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T144	1		T220	8		T152	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T138	14		T234	14		T280	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T190	12		T247	12		T283	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14739	1			T2	20		T3	1		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T13	4		T265	12		T306	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T240	4		T253	6		T227	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T14	1		T188	8		T176	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T137	8		T152	6		T226	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T229	7		T246	7		T260	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T137	7		T139	12		T223	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T206	11		T176	10		T211	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T8	3		T53	9		T135	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T15	7		T136	8		T56	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T305	1		T300	12		T358	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T56	11		T174	10		T146	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T138	14		T189	11		T155	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T20	2		T52	13		T164	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T258	9		T236	5		T166	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T136	14		T153	11		T191	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T18	1		T234	2		T176	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T139	12		T254	1		T238	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T28	1		T153	11		T154	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T144	13		T152	15		T225	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T138	17		T234	13		T280	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T247	6		T356	13		T359	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T166	9		T294	4		T90	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T13	4		T265	2		T290	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T138	14		T154	1		T280	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T144	1		T329	1		T283	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T169	1		T263	17		T92	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T48	1		T35	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T195	1		T240	7		T165	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	4		T14	5		T188	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	2		T157	17		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T19	7		T47	1		T233	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T137	21		T139	1		T223	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T54	1		T206	1		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T12	24		T17	1		T53	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T15	1		T151	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	6		T150	1		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T53	16		T138	2		T56	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T138	16		T189	5		T155	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T20	5		T52	1		T164	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T16	12		T140	16		T51	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T47	1		T156	4		T221	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T18	3		T163	1		T156	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T139	1		T142	1		T254	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T19	9		T150	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T220	8		T152	12		T225	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14678	1			T2	20		T3	1		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T138	17		T154	7		T280	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T144	13		T329	7		T357	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T360	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T240	4		T253	6		T227	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T13	4		T14	1		T188	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T226	19		T268	10		T182	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T229	7		T246	7		T260	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T137	8		T139	12		T223	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T206	11		T176	10		T334	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T53	9		T135	33		T137	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T15	7		T136	8		T56	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T8	3		T270	13		T305	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T56	11		T146	11		T229	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T138	14		T189	11		T155	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T20	2		T52	13		T164	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T267	11		T258	9		T236	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T221	2		T50	1		T136	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T18	1		T234	2		T176	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T139	12		T254	1		T246	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T28	1		T153	11		T234	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T152	15		T225	8		T251	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

auto[0]

4203

1

T8

3

T13

4

T14

1