Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23659

1

T2

20

T3

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17974

1

T2

20

T3

1

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

5685

1

T3

2

T12

24

T15

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17706

1

T2

20

T3

1

T4

13

auto[1]

5953

1

T3

2

T8

9

T12

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19765

1

T2

20

T3

2

T4

13

auto[1]

3894

1

T3

1

T8

3

T12

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	301	1			T139	13		T229	8		T165	1
values[0]	50	1			T53	15		T304	18		T307	17
values[1]	522	1			T19	9		T151	1		T157	17
values[2]	837	1			T14	6		T20	7		T47	1
values[3]	762	1			T17	1		T150	1		T49	4
values[4]	639	1			T19	7		T53	16		T48	1
values[5]	774	1			T13	8		T16	12		T18	4
values[6]	617	1			T15	8		T52	14		T163	1
values[7]	599	1			T3	2		T150	1		T164	26
values[8]	793	1			T47	1		T136	9		T222	1
values[9]	3087	1			T8	9		T12	24		T81	1
minimum	14678	1			T2	20		T3	1		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	583	1			T47	1		T151	1		T157	17
values[1]	3269	1			T12	24		T14	6		T20	7
values[2]	689	1			T17	1		T49	4		T158	1
values[3]	641	1			T18	4		T19	7		T53	16
values[4]	734	1			T15	8		T16	12		T163	1
values[5]	564	1			T13	8		T52	14		T136	9
values[6]	588	1			T3	2		T150	1		T164	26
values[7]	794	1			T47	1		T221	5		T136	9
values[8]	710	1			T8	9		T139	13		T56	22
values[9]	249	1			T229	8		T175	1		T224	22
minimum	14838	1			T2	20		T3	1		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

4203

1

T8

3

T13

4

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T206	12		T233	1		T253	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T47	1		T151	1		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T14	5		T20	5		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1714	1			T12	3		T81	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T17	1		T49	4		T189	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T158	1		T140	1		T51	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T18	3		T19	1		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T53	1		T156	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T16	1		T137	8		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T15	8		T163	1		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	5		T270	13		T305	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T52	14		T136	9		T139	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T150	1		T228	7		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	2		T164	13		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T221	3		T136	9		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T47	1		T188	9		T225	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	6		T56	12		T153	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T139	13		T152	16		T153	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T301	1		T177	3		T361	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T229	8		T175	1		T224	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14634	1			T2	20		T4	13		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T19	1		T231	1		T255	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T233	2		T310	11		T268	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T157	16		T50	1		T56	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T14	1		T20	2		T156	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1065	1			T12	21		T141	14		T248	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T189	4		T239	13		T249	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T140	15		T146	9		T216	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T18	1		T19	6		T174	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T53	15		T156	10		T137	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T16	11		T137	6		T152	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T229	10		T250	13		T232	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T13	3		T270	2		T305	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T220	7		T231	2		T264	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T228	9		T231	6		T247	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T164	13		T138	1		T226	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T221	2		T233	10		T232	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T188	2		T225	7		T250	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T8	3		T56	10		T153	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T152	11		T153	11		T240	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T301	1		T361	10		T312	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T224	12		T300	10		T178	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T3	1		T40	1		T53	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T19	8		T231	13		T105	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T165	1		T247	7		T261	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T139	13		T229	8		T175	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T53	10		T307	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T304	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T206	12		T233	1		T253	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T19	1		T151	1		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T14	5		T20	5		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T47	1		T50	4		T137	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T17	1		T49	4		T138	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T150	1		T140	1		T51	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T19	1		T48	1		T174	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T53	1		T158	1		T208	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T13	5		T16	1		T18	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T156	1		T54	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T270	13		T305	2		T308	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T15	8		T52	14		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T150	1		T191	4		T309	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	2		T164	13		T136	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T136	9		T222	1		T30	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T47	1		T225	9		T256	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	6		T221	3		T56	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1684	1			T12	3		T81	1		T141	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14582	1			T2	20		T4	13		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T247	11		T261	14		T281	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T224	12		T300	10		T302	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T53	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T304	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T233	2		T236	1		T310	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T19	8		T157	16		T56	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	1		T20	2		T156	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T50	1		T137	18		T223	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T138	15		T235	8		T239	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T140	15		T138	13		T28	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T19	6		T174	12		T189	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T53	15		T146	9		T229	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T13	3		T16	11		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T156	10		T137	1		T250	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T270	2		T305	3		T266	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T220	7		T229	10		T231	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T191	5		T330	9		T35	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T164	13		T138	1		T226	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T228	9		T231	6		T232	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T225	7		T250	11		T254	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	3		T221	2		T56	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1028	1			T12	21		T141	14		T248	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	1		T40	1		T216	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T206	1		T233	3		T253	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T47	1		T151	1		T157	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T14	5		T20	5		T156	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1397	1			T12	24		T81	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T17	1		T49	3		T189	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T158	1		T140	16		T51	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T18	3		T19	7		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T53	16		T156	11		T137	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T16	12		T137	7		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T15	1		T163	1		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	4		T270	3		T305	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T52	1		T136	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T150	1		T228	10		T231	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	2		T164	14		T138	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T221	3		T136	1		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T47	1		T188	3		T225	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T8	6		T56	11		T153	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T139	1		T152	12		T153	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T301	2		T177	1		T361	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T229	1		T175	1		T224	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14695	1			T2	20		T3	1		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T19	9		T231	14		T255	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T206	11		T253	13		T258	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T50	1		T136	14		T56	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T14	1		T20	2		T138	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1382	1			T135	33		T137	8		T138	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T49	1		T189	11		T237	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T146	11		T237	2		T316	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T18	1		T174	10		T234	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T229	13		T155	18		T251	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T137	7		T152	6		T234	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T15	7		T144	13		T229	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T13	4		T270	12		T305	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T52	13		T136	8		T139	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T228	6		T176	11		T247	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T164	12		T226	19		T241	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T221	2		T136	8		T154	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T188	8		T225	8		T256	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	3		T56	11		T153	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T139	12		T152	15		T153	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T177	2		T312	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T229	7		T224	9		T280	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T53	9		T177	2		T325	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T255	6		T105	12		T99	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T165	1		T247	12		T261	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T139	1		T229	1		T175	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T53	6		T307	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T304	18		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T206	1		T233	3		T253	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T19	9		T151	1		T157	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T14	5		T20	5		T156	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T47	1		T50	4		T137	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T17	1		T49	3		T138	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T150	1		T140	16		T51	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T19	7		T48	1		T174	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T53	16		T158	1		T208	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T13	4		T16	12		T18	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T156	11		T54	1		T137	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T270	3		T305	4		T308	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T15	1		T52	1		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T150	1		T191	6		T309	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	2		T164	14		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T136	1		T222	1		T30	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T47	1		T225	8		T256	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T8	6		T221	3		T56	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1366	1			T12	24		T81	1		T141	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14678	1			T2	20		T3	1		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T247	6		T177	2		T281	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T139	12		T229	7		T224	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T53	9		T307	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T206	11		T253	13		T258	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T136	14		T56	10		T176	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T14	1		T20	2		T227	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T50	1		T137	8		T223	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T49	1		T138	14		T166	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T138	17		T28	1		T267	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T174	10		T189	11		T234	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T146	11		T229	13		T155	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T13	4		T18	1		T137	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T144	13		T267	4		T262	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T270	12		T305	1		T266	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T15	7		T52	13		T139	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T191	3		T330	9		T313	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T164	12		T136	8		T226	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T136	8		T228	6		T232	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T225	8		T256	19		T254	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	3		T221	2		T56	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1346	1			T135	33		T252	27		T188	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

auto[0]

4203

1

T8

3

T13

4

T14

1