Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23659

1

T2

20

T3

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20008

1

T2

20

T3

1

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3651

1

T3

2

T8

9

T13

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17569

1

T2

20

T3

3

T4

13

auto[1]

6090

1

T8

9

T12

24

T14

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19765

1

T2

20

T3

2

T4

13

auto[1]

3894

1

T3

1

T8

3

T12

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	61	1			T220	8		T153	23		T99	14
values[0]	38	1			T362	7		T314	20		T296	11
values[1]	575	1			T14	6		T15	8		T20	7
values[2]	2873	1			T12	24		T81	1		T150	1
values[3]	769	1			T3	2		T16	12		T19	16
values[4]	705	1			T18	4		T54	1		T137	2
values[5]	621	1			T13	8		T52	14		T157	17
values[6]	750	1			T53	15		T136	9		T138	31
values[7]	640	1			T8	9		T164	26		T136	9
values[8]	686	1			T47	1		T49	4		T206	12
values[9]	1263	1			T17	1		T53	16		T48	1
minimum	14678	1			T2	20		T3	1		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	733	1			T14	6		T15	8		T20	7
values[1]	2851	1			T12	24		T19	9		T81	1
values[2]	811	1			T3	2		T16	12		T163	1
values[3]	535	1			T18	4		T19	7		T138	2
values[4]	743	1			T13	8		T52	14		T157	17
values[5]	725	1			T8	9		T53	15		T136	18
values[6]	580	1			T164	26		T229	26		T155	51
values[7]	792	1			T47	1		T49	4		T206	12
values[8]	1080	1			T17	1		T53	16		T48	1
values[9]	61	1			T69	3		T308	1		T316	1
minimum	14748	1			T2	20		T3	1		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

4203

1

T8

3

T13

4

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T20	5		T150	1		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T14	5		T15	8		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1623	1			T12	3		T81	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T19	1		T220	1		T195	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T16	1		T50	4		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	2		T163	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T18	3		T19	1		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T138	1		T166	13		T329	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T157	1		T231	1		T234	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	5		T52	14		T138	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T139	13		T222	1		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	6		T53	10		T136	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T229	14		T239	1		T287	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T164	13		T155	29		T175	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T206	12		T165	1		T245	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T47	1		T49	4		T222	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T53	1		T156	1		T137	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T17	1		T48	1		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T69	2		T316	1		T99	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T308	1		T317	1		T318	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14592	1			T2	20		T4	13		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T56	12		T246	8		T273	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T20	2		T28	2		T250	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T14	1		T146	9		T152	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	947	1			T12	21		T141	14		T248	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T19	8		T250	10		T270	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T16	11		T50	1		T137	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T138	15		T223	16		T153	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T18	1		T19	6		T239	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T138	1		T166	12		T328	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T157	16		T231	13		T234	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	3		T138	13		T189	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T228	9		T240	6		T234	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T8	3		T53	5		T140	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T229	12		T239	13		T333	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T164	13		T155	22		T246	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T245	1		T227	1		T267	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T166	15		T247	11		T230	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T53	15		T156	3		T137	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T156	10		T174	12		T153	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T69	1		T99	10		T363	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T317	3		T322	1		T319	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T3	1		T40	1		T216	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T56	10		T246	7		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T220	1		T99	4		T212	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T153	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T314	9		T296	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T362	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T20	5		T150	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T14	5		T15	8		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1624	1			T12	3		T81	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T163	1		T220	1		T195	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T16	1		T19	1		T50	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	2		T19	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T18	3		T137	1		T239	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T54	1		T138	1		T250	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T157	1		T165	1		T253	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T13	5		T52	14		T189	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T222	1		T174	1		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T53	10		T136	9		T138	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T139	13		T228	7		T240	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	6		T164	13		T136	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T206	12		T229	14		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T47	1		T49	4		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T53	1		T156	1		T137	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T17	1		T48	1		T156	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14582	1			T2	20		T4	13		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T220	7		T99	10		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T153	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T314	11		T296	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T362	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T20	2		T28	2		T250	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	1		T56	10		T146	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T12	21		T141	14		T248	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T250	10		T270	4		T211	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T16	11		T19	6		T50	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T19	8		T138	15		T223	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T18	1		T137	1		T239	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T138	1		T250	13		T236	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T157	16		T107	9		T268	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T13	3		T189	4		T225	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T231	13		T234	15		T190	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T53	5		T138	13		T152	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T228	9		T240	6		T239	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T8	3		T164	13		T140	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T229	12		T245	1		T227	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T166	15		T247	11		T264	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T53	15		T156	3		T137	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T156	10		T174	12		T233	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	1		T40	1		T216	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T20	5		T150	1		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T14	5		T15	1		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T12	24		T81	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T19	9		T220	1		T195	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T16	12		T50	4		T137	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	2		T163	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T18	3		T19	7		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T138	2		T166	13		T329	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T157	17		T231	14		T234	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T13	4		T52	1		T138	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T139	1		T222	1		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T8	6		T53	6		T136	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T229	13		T239	14		T287	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T164	14		T155	24		T175	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T206	1		T165	1		T245	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T47	1		T49	3		T222	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T53	16		T156	4		T137	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T17	1		T48	1		T156	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T69	3		T316	1		T99	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T308	1		T317	4		T318	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14691	1			T2	20		T3	1		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T56	11		T246	8		T273	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T20	2		T28	1		T154	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	1		T15	7		T136	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T221	2		T135	33		T137	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T251	7		T270	7		T211	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T50	1		T139	12		T188	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T138	14		T223	16		T153	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T18	1		T239	10		T232	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T166	12		T329	7		T255	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T234	2		T241	13		T268	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	4		T52	13		T138	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T139	12		T228	6		T240	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	3		T53	9		T136	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T229	13		T323	1		T333	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T164	12		T155	27		T246	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T206	11		T245	1		T227	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T49	1		T229	7		T166	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T137	8		T56	10		T232	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T144	13		T174	10		T153	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T99	3		T324	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T314	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T56	11		T246	7		T273	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T220	8		T99	11		T212	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T153	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T314	12		T296	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T362	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T20	5		T150	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	5		T15	1		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T12	24		T81	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T163	1		T220	1		T195	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T16	12		T19	7		T50	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	2		T19	9		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T18	3		T137	2		T239	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T54	1		T138	2		T250	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T157	17		T165	1		T253	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	4		T52	1		T189	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T222	1		T174	1		T231	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T53	6		T136	1		T138	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T139	1		T228	10		T240	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	6		T164	14		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T206	1		T229	13		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T47	1		T49	3		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	403	1			T53	16		T156	4		T137	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T17	1		T48	1		T156	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14678	1			T2	20		T3	1		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T99	3		T212	14		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T153	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T314	8		T296	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T362	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T20	2		T28	1		T154	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	1		T15	7		T136	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T221	2		T135	33		T137	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T253	13		T270	7		T211	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T50	1		T139	12		T188	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T138	14		T223	16		T153	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T18	1		T239	10		T232	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T236	11		T166	12		T246	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T253	6		T107	10		T268	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	4		T52	13		T189	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T234	15		T300	12		T335	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T53	9		T136	8		T138	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T139	12		T228	6		T240	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	3		T164	12		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T206	11		T229	13		T245	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T49	1		T166	17		T247	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T137	8		T56	10		T232	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T144	13		T174	10		T229	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

auto[0]

4203

1

T8

3

T13

4

T14

1