Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23659

1

T2

20

T3

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20265

1

T2

20

T3

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3394

1

T13

8

T14

6

T15

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17368

1

T2

20

T3

3

T4

13

auto[1]

6291

1

T12

24

T15

8

T16

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19765

1

T2

20

T3

2

T4

13

auto[1]

3894

1

T3

1

T8

3

T12

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	64	1			T251	8		T247	18		T326	17
values[0]	98	1			T48	1		T169	1		T348	5
values[1]	501	1			T3	2		T13	8		T14	6
values[2]	493	1			T19	7		T47	1		T157	17
values[3]	711	1			T53	15		T54	1		T206	12
values[4]	3090	1			T12	24		T15	8		T17	1
values[5]	595	1			T8	9		T53	16		T150	1
values[6]	719	1			T20	7		T164	26		T49	4
values[7]	795	1			T47	1		T52	14		T156	4
values[8]	659	1			T16	12		T18	4		T163	1
values[9]	1256	1			T19	9		T150	1		T158	1
minimum	14678	1			T2	20		T3	1		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	616	1			T3	2		T13	8		T14	6
values[1]	602	1			T54	1		T137	27		T222	1
values[2]	816	1			T157	17		T206	12		T137	16
values[3]	2984	1			T8	9		T12	24		T15	8
values[4]	536	1			T53	16		T56	22		T174	1
values[5]	899	1			T20	7		T47	1		T52	14
values[6]	550	1			T163	1		T156	15		T136	15
values[7]	752	1			T16	12		T18	4		T19	9
values[8]	874	1			T150	1		T144	14		T220	8
values[9]	302	1			T138	31		T251	8		T234	27
minimum	14728	1			T2	20		T3	1		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

4203

1

T8

3

T13

4

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	2		T240	5		T165	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	5		T14	5		T19	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T137	9		T220	1		T152	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T54	1		T222	1		T233	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T157	1		T137	9		T139	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T206	12		T208	1		T216	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1627	1			T8	6		T12	3		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T15	8		T151	1		T136	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T174	1		T305	3		T355	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T53	1		T56	12		T146	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T221	3		T138	15		T189	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T20	5		T47	1		T52	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T163	1		T156	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T156	1		T136	15		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T16	1		T18	3		T19	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T139	13		T142	1		T254	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T150	1		T28	4		T153	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T144	14		T220	1		T152	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T138	18		T234	14		T280	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T251	8		T190	1		T247	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14608	1			T2	20		T4	13		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T265	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T240	6		T227	1		T166	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	3		T14	1		T19	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T137	18		T152	6		T226	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T233	11		T229	10		T250	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T157	16		T137	7		T223	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T216	1		T235	8		T250	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T8	3		T12	21		T53	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T138	1		T56	8		T174	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T305	3		T355	13		T364	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T53	15		T56	10		T146	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T221	2		T138	15		T189	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T20	2		T164	13		T50	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T156	10		T140	15		T231	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T156	3		T153	11		T233	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T16	11		T18	1		T19	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T254	1		T246	15		T244	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T28	2		T153	11		T231	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T220	7		T152	11		T225	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T138	13		T234	13		T170	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T190	11		T247	11		T356	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T3	1		T40	1		T216	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T265	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T326	17		T365	1		T313	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T251	8		T247	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T169	1		T263	1		T92	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T48	1		T348	2		T306	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	2		T240	5		T165	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	5		T14	5		T188	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T157	1		T226	20		T196	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T19	1		T47	1		T233	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T53	10		T137	10		T139	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T54	1		T206	12		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1670	1			T12	3		T17	1		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T15	8		T136	9		T56	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T8	6		T150	1		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T53	1		T151	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T140	1		T138	15		T189	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T20	5		T164	13		T49	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T221	3		T51	2		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T47	1		T52	14		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T16	1		T18	3		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T142	1		T152	16		T254	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	448	1			T19	1		T150	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T144	14		T220	1		T225	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14582	1			T2	20		T4	13		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T313	13		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T247	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T263	16		T92	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T348	3		T306	1		T35	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T240	6		T227	1		T166	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T13	3		T14	1		T188	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T157	16		T226	13		T268	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T19	6		T233	11		T229	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T53	5		T137	19		T152	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T235	8		T250	24		T236	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T12	21		T141	14		T248	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T56	8		T174	12		T216	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	3		T233	10		T270	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T53	15		T138	1		T56	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T140	15		T138	15		T189	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T20	2		T164	13		T245	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T221	2		T231	2		T267	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T156	3		T50	1		T153	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T16	11		T18	1		T156	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T152	11		T254	1		T241	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T19	8		T138	13		T28	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T220	7		T225	7		T190	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	1		T40	1		T216	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	2		T240	7		T165	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	4		T14	5		T19	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T137	19		T220	1		T152	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T54	1		T222	1		T233	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T157	17		T137	9		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T206	1		T208	1		T216	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T8	6		T12	24		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	1		T151	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T174	1		T305	5		T355	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T53	16		T56	11		T146	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T221	3		T138	16		T189	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T20	5		T47	1		T52	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T163	1		T156	11		T140	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T156	4		T136	1		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T16	12		T18	3		T19	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T139	1		T142	1		T254	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T150	1		T28	5		T153	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T144	1		T220	8		T152	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T138	14		T234	14		T280	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T251	1		T190	12		T247	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14691	1			T2	20		T3	1		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T265	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T240	4		T253	6		T227	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	4		T14	1		T188	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T137	8		T152	6		T226	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T229	7		T246	7		T260	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T137	7		T139	12		T223	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T206	11		T176	10		T211	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T8	3		T53	9		T135	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T15	7		T136	8		T56	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T305	1		T300	12		T358	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T56	11		T146	11		T229	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T221	2		T138	14		T189	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T20	2		T52	13		T164	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T258	9		T236	5		T166	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T136	14		T153	11		T237	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T18	1		T234	2		T176	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T139	12		T254	1		T246	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T28	1		T153	11		T154	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T144	13		T152	15		T225	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T138	17		T234	13		T280	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T251	7		T247	6		T356	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T366	18		T360	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T265	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T326	1		T365	1		T313	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T251	1		T247	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T169	1		T263	17		T92	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T48	1		T348	4		T306	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T3	2		T240	7		T165	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	4		T14	5		T188	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T157	17		T226	14		T196	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T19	7		T47	1		T233	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T53	6		T137	21		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T54	1		T206	1		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T12	24		T17	1		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T15	1		T136	1		T56	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T8	6		T150	1		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T53	16		T151	1		T138	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T140	16		T138	16		T189	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T20	5		T164	14		T49	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T221	3		T51	2		T231	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T47	1		T52	1		T156	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T16	12		T18	3		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T142	1		T152	12		T254	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T19	9		T150	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T144	1		T220	8		T225	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14678	1			T2	20		T3	1		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T326	16		T313	6		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T251	7		T247	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T366	18		T360	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T348	1		T367	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T240	4		T253	6		T227	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T13	4		T14	1		T188	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T226	19		T268	10		T182	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T229	7		T246	7		T260	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T53	9		T137	8		T139	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T206	11		T198	2		T368	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T135	33		T137	7		T252	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T15	7		T136	8		T56	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T8	3		T270	13		T305	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T56	11		T146	11		T229	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T138	14		T189	11		T155	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T20	2		T164	12		T49	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T221	2		T267	11		T236	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T52	13		T50	1		T136	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T18	1		T234	2		T176	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T152	15		T254	1		T246	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	380	1			T138	17		T28	1		T153	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T144	13		T225	8		T238	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

auto[0]

4203

1

T8

3

T13

4

T14

1