Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T158	1		T195	1		T254	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T222	2		T152	16		T255	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T48	1		T153	12		T229	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	6		T20	5		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	2		T13	5		T14	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T150	1		T137	8		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T47	1		T139	13		T233	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T17	1		T54	1		T221	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T19	1		T49	4		T139	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T156	1		T138	1		T222	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1569	1			T12	3		T81	1		T141	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T15	8		T137	1		T249	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T53	10		T164	13		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T18	3		T52	14		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T53	1		T137	9		T138	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T155	10		T224	10		T241	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T138	18		T56	11		T174	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T163	1		T151	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T19	1		T206	12		T51	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T136	15		T140	1		T58	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14582	1			T2	20		T4	13		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T254	1		T262	7		T263	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T152	11		T264	10		T230	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T153	11		T229	10		T232	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T8	3		T20	2		T156	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	3		T14	1		T16	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T137	6		T146	9		T245	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T233	10		T234	2		T239	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T221	2		T50	1		T100	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T19	6		T223	16		T152	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T156	3		T138	1		T224	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	869	1			T12	21		T141	14		T248	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T137	1		T249	12		T246	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T53	5		T164	13		T225	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T18	1		T238	2		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T53	15		T137	18		T138	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T155	9		T224	12		T241	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T138	13		T56	8		T174	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T157	16		T56	10		T220	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T19	8		T216	1		T240	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T140	15		T231	15		T234	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	1		T40	1		T216	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	2		T16	12		T48	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T8	6		T20	5		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T13	4		T14	5		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T54	1		T50	4		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T49	3		T154	1		T233	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T17	1		T221	3		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T12	24		T19	7		T81	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T156	4		T222	1		T224	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T225	8		T227	2		T258	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T15	1		T52	1		T137	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T53	22		T164	14		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T18	3		T150	1		T155	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T137	19		T138	16		T28	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T157	17		T229	13		T239	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T51	2		T138	14		T56	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T163	1		T151	1		T56	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T19	9		T158	1		T206	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T136	1		T140	16		T222	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T195	1		T242	9		T192	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T152	12		T231	14		T244	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14727	1			T2	20		T3	1		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T47	1		T156	11		T166	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T176	6		T265	2		T266	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	3		T20	2		T137	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	4		T14	1		T139	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T50	1		T136	8		T107	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T49	1		T154	7		T234	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T221	2		T136	8		T144	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T135	33		T139	12		T252	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T224	2		T236	5		T247	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T225	8		T227	18		T258	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T15	7		T52	13		T238	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T53	9		T164	12		T189	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T18	1		T155	9		T260	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T137	8		T138	14		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T229	13		T224	9		T241	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T138	17		T56	10		T174	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T56	11		T237	11		T191	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T206	11		T240	4		T254	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T136	14		T234	13		T267	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T242	9		T192	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T152	15		T107	11		T268	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T153	11		T229	7		T256	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T166	12		T269	15		T213	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T158	1		T195	1		T254	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T222	2		T152	12		T255	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T48	1		T153	12		T229	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	6		T20	5		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	2		T13	4		T14	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T150	1		T137	7		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T47	1		T139	1		T233	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T17	1		T54	1		T221	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T19	7		T49	3		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T156	4		T138	2		T222	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1181	1			T12	24		T81	1		T141	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	1		T137	2		T249	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T53	6		T164	14		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T18	3		T52	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T53	16		T137	19		T138	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T155	10		T224	13		T241	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T138	14		T56	9		T174	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T163	1		T151	1		T157	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T19	9		T206	1		T51	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T136	1		T140	16		T58	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14678	1			T2	20		T3	1		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T254	1		T262	12		T242	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T152	15		T255	26		T107	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T153	11		T229	7		T256	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T8	3		T20	2		T166	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	4		T14	1		T188	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T137	7		T146	11		T245	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T139	12		T234	2		T239	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T221	2		T50	1		T136	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T49	1		T139	12		T223	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T224	2		T236	5		T247	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T135	33		T252	27		T257	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T15	7		T246	7		T270	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T53	9		T164	12		T225	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T18	1		T52	13		T238	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T137	8		T138	14		T28	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T155	9		T224	9		T241	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T138	17		T56	10		T174	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T56	11		T229	13		T237	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T206	11		T240	4		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T136	14		T234	13		T267	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

auto[0]

4203

1

T8

3

T13

4

T14

1