Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23659

1

T2

20

T3

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20373

1

T2

20

T3

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3286

1

T14

6

T15

8

T16

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17767

1

T2

20

T3

3

T4

13

auto[1]

5892

1

T8

9

T12

24

T14

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19765

1

T2

20

T3

2

T4

13

auto[1]

3894

1

T3

1

T8

3

T12

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T88	1		T271	1		-	-
values[0]	42	1			T175	1		T272	3		T273	12
values[1]	772	1			T8	9		T14	6		T53	31
values[2]	523	1			T52	14		T150	1		T138	2
values[3]	772	1			T20	7		T156	11		T54	1
values[4]	825	1			T15	8		T220	8		T152	27
values[5]	783	1			T19	16		T150	1		T48	1
values[6]	813	1			T47	1		T136	15		T139	13
values[7]	619	1			T18	4		T47	1		T158	1
values[8]	2781	1			T3	2		T12	24		T16	12
values[9]	1049	1			T13	8		T151	1		T49	4
minimum	14678	1			T2	20		T3	1		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	899	1			T8	9		T14	6		T53	16
values[1]	634	1			T20	7		T52	14		T156	11
values[2]	787	1			T15	8		T157	17		T137	27
values[3]	797	1			T19	9		T152	27		T233	3
values[4]	770	1			T19	7		T47	1		T150	1
values[5]	696	1			T136	15		T208	1		T188	11
values[6]	2999	1			T12	24		T16	12		T17	1
values[7]	561	1			T3	2		T13	8		T163	1
values[8]	664	1			T151	1		T49	4		T136	9
values[9]	156	1			T136	9		T51	2		T144	14
minimum	14696	1			T2	20		T3	1		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

4203

1

T8

3

T13

4

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T8	6		T53	1		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T14	5		T156	1		T146	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T52	14		T156	1		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T20	5		T54	1		T138	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T220	1		T233	1		T155	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T15	8		T157	1		T137	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T229	8		T232	3		T258	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T19	1		T152	16		T233	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T19	1		T150	1		T164	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T47	1		T48	1		T221	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T208	1		T188	9		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T136	15		T174	11		T250	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1682	1			T12	3		T17	1		T81	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T16	1		T18	3		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T3	2		T13	5		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T163	1		T222	1		T223	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T151	1		T49	4		T136	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T206	12		T229	8		T245	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T51	2		T144	14		T262	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T136	9		T153	12		T275	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14594	1			T2	20		T4	13		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T276	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T8	3		T53	15		T138	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	1		T156	3		T146	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T156	10		T234	13		T254	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T20	2		T138	13		T152	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T220	7		T233	11		T155	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T157	16		T137	18		T228	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T232	2		T236	10		T249	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T19	8		T152	11		T233	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T19	6		T164	13		T28	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T221	2		T50	1		T224	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T188	2		T153	11		T246	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T174	12		T250	24		T241	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T12	21		T141	14		T248	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T16	11		T18	1		T229	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	3		T140	15		T56	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T223	16		T233	10		T241	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T137	1		T138	15		T56	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T229	10		T245	1		T227	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T262	6		T277	4		T92	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T153	11		T278	5		T203	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T3	1		T40	1		T53	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T271	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T88	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T175	1		T279	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T272	3		T273	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	6		T53	11		T226	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T14	5		T156	1		T189	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T52	14		T150	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T146	12		T239	11		T237	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T156	1		T155	19		T231	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T20	5		T54	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T220	1		T233	1		T229	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T15	8		T152	16		T228	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T19	1		T150	1		T164	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T19	1		T48	1		T221	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T174	1		T216	4		T195	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T47	1		T136	15		T139	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T158	1		T208	1		T188	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T18	3		T47	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1609	1			T3	2		T12	3		T17	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T16	1		T163	1		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T13	5		T151	1		T49	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T136	9		T206	12		T223	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14582	1			T2	20		T4	13		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T279	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T8	3		T53	20		T226	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	1		T156	3		T189	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T138	1		T234	13		T236	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T146	9		T239	7		T237	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T156	10		T155	13		T231	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T20	2		T157	16		T137	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T220	7		T233	11		T232	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T152	11		T228	9		T240	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T19	6		T164	13		T28	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T19	8		T221	2		T50	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T216	1		T246	15		T268	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T174	12		T250	24		T241	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T188	2		T153	11		T107	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T18	1		T229	12		T167	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T12	21		T141	14		T248	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T16	11		T241	15		T171	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	3		T137	1		T138	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T223	16		T153	11		T233	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	1		T40	1		T216	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T8	6		T53	16		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T14	5		T156	4		T146	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T52	1		T156	11		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T20	5		T54	1		T138	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T220	8		T233	12		T155	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T15	1		T157	17		T137	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T229	1		T232	3		T258	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T19	9		T152	12		T233	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T19	7		T150	1		T164	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T47	1		T48	1		T221	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T208	1		T188	3		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T136	1		T174	13		T250	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T12	24		T17	1		T81	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T16	12		T18	3		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	2		T13	4		T140	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T163	1		T222	1		T223	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T151	1		T49	3		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T206	1		T229	11		T245	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T51	2		T144	1		T262	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T136	1		T153	12		T275	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14686	1			T2	20		T3	1		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T276	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T8	3		T226	19		T234	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T14	1		T146	11		T189	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T52	13		T234	13		T254	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T20	2		T138	17		T152	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T155	18		T253	13		T224	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T15	7		T137	8		T228	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T229	7		T232	2		T258	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T152	15		T240	4		T280	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T164	12		T139	12		T28	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T221	2		T50	1		T139	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T188	8		T153	11		T251	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T136	14		T174	10		T105	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T135	33		T137	7		T252	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T18	1		T229	13		T260	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T13	4		T56	10		T253	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T223	16		T241	13		T280	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T49	1		T136	8		T138	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T206	11		T229	7		T245	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T144	13		T262	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T136	8		T153	11		T281	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T53	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T271	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T88	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T175	1		T279	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T272	3		T273	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T8	6		T53	22		T226	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	5		T156	4		T189	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T52	1		T150	1		T138	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T146	10		T239	8		T237	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T156	11		T155	14		T231	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T20	5		T54	1		T157	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T220	8		T233	12		T229	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T15	1		T152	12		T228	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T19	7		T150	1		T164	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T19	9		T48	1		T221	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T174	1		T216	5		T195	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T47	1		T136	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T158	1		T208	1		T188	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T18	3		T47	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T3	2		T12	24		T17	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T16	12		T163	1		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T13	4		T151	1		T49	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T136	1		T206	1		T223	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14678	1			T2	20		T3	1		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T279	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T273	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	3		T53	9		T226	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	1		T189	11		T225	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T52	13		T234	13		T236	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T146	11		T239	10		T237	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T155	18		T253	13		T224	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T20	2		T137	8		T138	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T229	7		T232	2		T258	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T15	7		T152	15		T228	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T164	12		T139	12		T28	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T221	2		T50	1		T166	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T251	7		T256	19		T246	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T136	14		T139	12		T174	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T188	8		T153	11		T154	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T18	1		T229	13		T260	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T135	33		T137	7		T252	27
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T241	13		T280	6		T201	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	4		T49	1		T136	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T136	8		T206	11		T223	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

auto[0]

4203

1

T8

3

T13

4

T14

1