Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23659

1

T2

20

T3

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20462

1

T2

20

T3

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3197

1

T14

6

T15

8

T16

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17763

1

T2

20

T3

3

T4

13

auto[1]

5896

1

T8

9

T12

24

T14

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19765

1

T2

20

T3

2

T4

13

auto[1]

3894

1

T3

1

T8

3

T12

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	128	1			T151	1		T153	23		T245	3
values[0]	3	1			T272	3		-	-		-	-
values[1]	834	1			T8	9		T14	6		T53	31
values[2]	533	1			T52	14		T150	1		T156	11
values[3]	712	1			T20	7		T54	1		T157	17
values[4]	866	1			T15	8		T19	9		T220	8
values[5]	751	1			T19	7		T150	1		T48	1
values[6]	746	1			T47	1		T136	15		T139	13
values[7]	706	1			T16	12		T17	1		T18	4
values[8]	2779	1			T3	2		T12	24		T81	1
values[9]	923	1			T13	8		T49	4		T136	18
minimum	14678	1			T2	20		T3	1		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	726	1			T8	9		T14	6		T53	16
values[1]	644	1			T20	7		T52	14		T156	11
values[2]	754	1			T15	8		T157	17		T137	27
values[3]	878	1			T19	9		T220	8		T152	27
values[4]	658	1			T19	7		T47	1		T150	1
values[5]	777	1			T136	15		T208	1		T188	11
values[6]	2963	1			T12	24		T16	12		T17	1
values[7]	571	1			T3	2		T13	8		T163	1
values[8]	718	1			T136	9		T206	12		T137	2
values[9]	124	1			T151	1		T136	9		T144	14
minimum	14846	1			T2	20		T3	1		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

4203

1

T8

3

T13

4

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	6		T53	1		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	5		T156	1		T146	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T52	14		T156	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T20	5		T54	1		T138	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T233	1		T155	19		T231	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T15	8		T157	1		T137	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T19	1		T220	1		T229	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T152	16		T233	1		T282	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T19	1		T150	1		T164	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T47	1		T48	1		T221	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T136	15		T208	1		T188	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T174	11		T250	2		T241	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1660	1			T12	3		T17	1		T81	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T16	1		T18	3		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	2		T13	5		T49	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T163	1		T222	1		T223	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T136	9		T137	1		T51	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T206	12		T229	8		T245	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T151	1		T136	9		T144	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T153	12		T283	1		T278	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14615	1			T2	20		T4	13		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T225	9		T265	1		T272	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	3		T53	15		T189	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	1		T156	3		T146	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T156	10		T138	1		T234	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T20	2		T138	13		T152	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T233	11		T155	13		T231	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T157	16		T137	18		T264	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T19	8		T220	7		T232	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T152	11		T233	2		T228	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T19	6		T164	13		T28	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T221	2		T50	1		T166	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T188	2		T153	11		T246	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T174	12		T250	24		T241	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T12	21		T141	14		T248	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T16	11		T18	1		T229	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	3		T140	15		T56	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T223	16		T233	10		T241	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T137	1		T138	15		T56	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T229	10		T245	1		T227	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T262	6		T277	4		T92	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T153	11		T278	5		T284	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	1		T40	1		T53	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T225	7		T265	6		T285	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T151	1		T270	8		T97	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T153	12		T245	2		T286	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T272	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	6		T53	11		T189	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T14	5		T156	1		T146	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T52	14		T150	1		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T152	7		T239	11		T237	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T155	19		T231	1		T287	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T20	5		T54	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T19	1		T220	1		T233	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T15	8		T152	16		T282	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T19	1		T150	1		T164	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T48	1		T221	3		T50	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T136	15		T208	1		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T47	1		T139	13		T174	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T17	1		T158	1		T188	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T16	1		T18	3		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1607	1			T3	2		T12	3		T81	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T163	1		T222	1		T175	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T13	5		T49	4		T136	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T206	12		T223	17		T233	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14582	1			T2	20		T4	13		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T270	4		T97	11		T262	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T153	11		T245	1		T278	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T8	3		T53	20		T189	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	1		T156	3		T146	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T156	10		T138	1		T234	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T152	6		T239	7		T237	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T155	13		T231	13		T224	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T20	2		T157	16		T137	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T19	8		T220	7		T233	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T152	11		T228	9		T240	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T19	6		T164	13		T28	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T221	2		T50	1		T233	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T246	15		T268	12		T288	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T174	12		T250	24		T241	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T188	2		T153	11		T261	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T16	11		T18	1		T229	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T12	21		T141	14		T248	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T241	15		T260	13		T171	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	3		T137	1		T138	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T223	16		T233	10		T229	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	1		T40	1		T216	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T8	6		T53	16		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	5		T156	4		T146	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T52	1		T156	11		T138	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T20	5		T54	1		T138	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T233	12		T155	14		T231	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	1		T157	17		T137	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T19	9		T220	8		T229	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T152	12		T233	3		T282	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T19	7		T150	1		T164	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T47	1		T48	1		T221	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T136	1		T208	1		T188	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T174	13		T250	26		T241	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T12	24		T17	1		T81	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T16	12		T18	3		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	2		T13	4		T49	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T163	1		T222	1		T223	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T136	1		T137	2		T51	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T206	1		T229	11		T245	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T151	1		T136	1		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T153	12		T283	1		T278	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14728	1			T2	20		T3	1		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T225	8		T265	7		T272	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	3		T189	11		T226	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	1		T146	11		T238	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T52	13		T234	13		T166	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T20	2		T138	17		T152	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T155	18		T224	9		T176	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T15	7		T137	8		T253	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T229	7		T232	2		T258	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T152	15		T228	6		T240	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T164	12		T139	12		T28	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T221	2		T50	1		T139	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T136	14		T188	8		T153	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T174	10		T105	12		T191	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T135	33		T137	7		T252	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T18	1		T229	13		T211	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T13	4		T49	1		T56	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T223	16		T241	13		T260	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T136	8		T138	14		T56	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T206	11		T229	7		T245	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T136	8		T144	13		T262	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T153	11		T278	8		T284	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T53	9		T234	2		T270	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T225	8		T285	15		T204	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T151	1		T270	5		T97	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T153	12		T245	2		T286	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T272	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T8	6		T53	22		T189	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T14	5		T156	4		T146	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T52	1		T150	1		T156	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T152	7		T239	8		T237	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T155	14		T231	14		T287	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T20	5		T54	1		T157	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T19	9		T220	8		T233	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T15	1		T152	12		T282	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T19	7		T150	1		T164	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T48	1		T221	3		T50	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T136	1		T208	1		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T47	1		T139	1		T174	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T17	1		T158	1		T188	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T16	12		T18	3		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T3	2		T12	24		T81	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T163	1		T222	1		T175	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T13	4		T49	3		T136	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T206	1		T223	17		T233	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14678	1			T2	20		T3	1		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T270	7		T262	7		T289	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T153	11		T245	1		T278	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	3		T53	9		T189	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	1		T146	11		T225	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T52	13		T234	13		T236	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T152	6		T239	10		T237	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T155	18		T224	9		T176	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T20	2		T137	8		T138	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T229	7		T232	2		T258	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T15	7		T152	15		T228	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T164	12		T139	12		T28	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T221	2		T50	1		T166	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T136	14		T251	7		T256	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T139	12		T174	10		T105	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T188	8		T153	11		T154	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T18	1		T229	13		T211	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T135	33		T137	7		T252	27
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T241	13		T260	2		T201	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	4		T49	1		T136	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T206	11		T223	16		T229	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

auto[0]

4203

1

T8

3

T13

4

T14

1