Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23659

1

T2

20

T3

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19984

1

T2

20

T3

1

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3675

1

T3

2

T8

9

T13

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17420

1

T2

20

T3

1

T4

13

auto[1]

6239

1

T3

2

T8

9

T12

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19765

1

T2

20

T3

2

T4

13

auto[1]

3894

1

T3

1

T8

3

T12

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	392	1			T14	4		T40	2		T18	2
values[0]	41	1			T28	6		T290	1		T291	1
values[1]	648	1			T54	1		T136	9		T206	12
values[2]	2957	1			T12	24		T19	9		T53	16
values[3]	849	1			T137	41		T233	11		T195	1
values[4]	646	1			T150	1		T49	4		T139	13
values[5]	709	1			T14	6		T18	4		T52	14
values[6]	593	1			T8	9		T15	8		T19	7
values[7]	660	1			T3	2		T16	12		T20	7
values[8]	520	1			T13	8		T139	13		T174	1
values[9]	1310	1			T17	1		T47	1		T150	1
minimum	14334	1			T2	20		T3	1		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	885	1			T54	1		T136	9		T206	12
values[1]	2947	1			T12	24		T19	9		T81	1
values[2]	848	1			T53	16		T137	41		T152	27
values[3]	561	1			T150	1		T49	4		T189	16
values[4]	723	1			T14	6		T18	4		T19	7
values[5]	624	1			T8	9		T15	8		T16	12
values[6]	526	1			T3	2		T20	7		T53	15
values[7]	646	1			T13	8		T139	13		T140	16
values[8]	1026	1			T17	1		T47	1		T48	1
values[9]	195	1			T150	1		T229	8		T240	11
minimum	14678	1			T2	20		T3	1		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

4203

1

T8

3

T13

4

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T206	12		T274	1		T175	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T54	1		T136	9		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1636	1			T12	3		T81	1		T141	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T19	1		T234	3		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T225	9		T233	1		T195	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T53	1		T137	17		T152	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T150	1		T49	4		T189	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T228	7		T231	1		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T156	1		T221	3		T136	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T14	5		T18	3		T19	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	8		T16	1		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	6		T163	1		T253	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T20	5		T53	10		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	2		T157	1		T195	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T138	15		T220	1		T253	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	5		T139	13		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T156	1		T158	1		T174	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T17	1		T47	1		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T150	1		T166	10		T200	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T229	8		T240	5		T224	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14582	1			T2	20		T4	13		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T239	7		T227	1		T190	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T28	2		T153	11		T155	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T12	21		T141	14		T164	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T19	8		T234	2		T260	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T225	7		T233	10		T250	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T53	15		T137	24		T152	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T189	4		T226	13		T292	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T228	9		T231	13		T236	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T156	10		T221	2		T223	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	1		T18	1		T19	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T16	11		T146	9		T220	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T8	3		T254	1		T241	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T20	2		T53	5		T137	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T157	16		T235	8		T230	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T138	15		T250	13		T236	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	3		T140	15		T153	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T156	3		T174	12		T229	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T50	1		T56	18		T216	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T166	3		T200	12		T278	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T240	6		T224	12		T293	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	1		T40	1		T216	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T14	4		T40	2		T18	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T294	5		T295	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T290	1		T296	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T28	4		T291	1		T297	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T206	12		T175	1		T239	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T54	1		T136	9		T153	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1652	1			T12	3		T81	1		T141	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T19	1		T53	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T233	1		T195	1		T250	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T137	17		T228	7		T234	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T150	1		T49	4		T139	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T51	2		T152	16		T154	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T156	1		T222	1		T189	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	5		T18	3		T52	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	8		T221	3		T136	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	6		T19	1		T138	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T16	1		T20	5		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	2		T163	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T220	1		T253	14		T236	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	5		T139	13		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T150	1		T156	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T17	1		T47	1		T48	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14238	1			T2	20		T4	13		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T243	1		T277	4		T298	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T296	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T28	2		T297	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T239	7		T227	1		T190	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T153	11		T155	9		T231	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T12	21		T141	14		T164	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T19	8		T53	15		T234	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T233	10		T250	10		T267	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T137	24		T228	9		T234	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T226	13		T237	12		T244	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T152	11		T231	13		T236	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T156	10		T189	4		T223	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T14	1		T18	1		T138	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T221	2		T188	2		T220	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T8	3		T19	6		T138	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T16	11		T20	2		T53	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T157	16		T140	15		T235	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T236	9		T247	11		T107	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T13	3		T233	11		T249	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T156	3		T138	15		T174	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T50	1		T56	18		T216	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	1		T40	1		T216	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T206	1		T274	1		T175	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T54	1		T136	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T12	24		T81	1		T141	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T19	9		T234	3		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T225	8		T233	11		T195	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T53	16		T137	26		T152	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T150	1		T49	3		T189	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T228	10		T231	14		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T156	11		T221	3		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	5		T18	3		T19	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	1		T16	12		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T8	6		T163	1		T253	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T20	5		T53	6		T137	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	2		T157	17		T195	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T138	16		T220	1		T253	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	4		T139	1		T140	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T156	4		T158	1		T174	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T17	1		T47	1		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T150	1		T166	4		T200	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T229	1		T240	7		T224	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14678	1			T2	20		T3	1		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T206	11		T239	10		T227	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T136	8		T28	1		T153	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T164	12		T135	33		T136	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T234	2		T176	10		T280	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T225	8		T267	4		T247	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T137	15		T152	15		T154	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T49	1		T189	11		T226	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T228	6		T258	9		T236	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T221	2		T136	8		T139	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	1		T18	1		T52	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T15	7		T146	11		T152	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	3		T253	6		T254	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T20	2		T53	9		T188	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T211	8		T299	11		T198	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T138	14		T253	13		T236	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	4		T139	12		T153	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T174	10		T229	7		T166	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T50	1		T56	21		T155	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T166	9		T200	12		T281	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T229	7		T240	4		T224	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T14	4		T40	2		T18	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T294	1		T295	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T290	1		T296	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T28	5		T291	1		T297	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T206	1		T175	1		T239	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T54	1		T136	1		T153	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T12	24		T81	1		T141	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T19	9		T53	16		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T233	11		T195	1		T250	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T137	26		T228	10		T234	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T150	1		T49	3		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T51	2		T152	12		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T156	11		T222	1		T189	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	5		T18	3		T52	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T15	1		T221	3		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	6		T19	7		T138	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T16	12		T20	5		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T3	2		T163	1		T157	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T220	1		T253	1		T236	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T13	4		T139	1		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T150	1		T156	4		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	453	1			T17	1		T47	1		T48	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14334	1			T2	20		T3	1		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T243	1		T298	12		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T294	4		T295	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T296	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T28	1		T297	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T206	11		T239	10		T227	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T136	8		T153	11		T155	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T164	12		T135	33		T136	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T234	2		T245	1		T176	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T267	4		T247	9		T237	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T137	15		T228	6		T234	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T49	1		T139	12		T226	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T152	15		T154	7		T251	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T189	11		T223	16		T224	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	1		T18	1		T52	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T15	7		T221	2		T136	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T8	3		T138	17		T229	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T20	2		T53	9		T146	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T254	1		T246	2		T211	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T253	13		T236	11		T176	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T13	4		T139	12		T300	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T138	14		T174	10		T229	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T50	1		T56	21		T153	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

auto[0]

4203

1

T8

3

T13

4

T14

1