Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23659

1

T2

20

T3

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20018

1

T2

20

T3

1

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3641

1

T3

2

T8

9

T13

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17563

1

T2

20

T3

3

T4

13

auto[1]

6096

1

T8

9

T12

24

T14

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19765

1

T2

20

T3

2

T4

13

auto[1]

3894

1

T3

1

T8

3

T12

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	398	1			T53	16		T156	15		T208	1
values[0]	25	1			T315	14		T296	11		-	-
values[1]	631	1			T14	6		T15	8		T20	7
values[2]	2881	1			T12	24		T81	1		T150	1
values[3]	724	1			T3	2		T16	12		T19	16
values[4]	664	1			T18	4		T54	1		T137	2
values[5]	694	1			T13	8		T52	14		T157	17
values[6]	691	1			T53	15		T136	9		T138	31
values[7]	688	1			T8	9		T164	26		T136	9
values[8]	671	1			T47	1		T49	4		T206	12
values[9]	914	1			T17	1		T48	1		T137	27
minimum	14678	1			T2	20		T3	1		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	540	1			T14	6		T15	8		T47	1
values[1]	2860	1			T12	24		T81	1		T141	16
values[2]	827	1			T3	2		T16	12		T19	9
values[3]	531	1			T18	4		T19	7		T138	2
values[4]	758	1			T13	8		T52	14		T157	17
values[5]	625	1			T8	9		T53	15		T136	18
values[6]	662	1			T164	26		T140	16		T174	1
values[7]	797	1			T47	1		T49	4		T206	12
values[8]	1009	1			T53	16		T48	1		T156	15
values[9]	109	1			T17	1		T69	3		T316	1
minimum	14941	1			T2	20		T3	1		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

4203

1

T8

3

T13

4

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T150	2		T158	1		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	5		T15	8		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1645	1			T12	3		T81	1		T141	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T220	1		T195	1		T30	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T16	1		T50	4		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T3	2		T19	1		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T18	3		T19	1		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T138	1		T195	1		T236	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T157	1		T231	1		T234	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T13	5		T52	14		T138	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T139	13		T222	1		T228	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	6		T53	10		T136	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T174	1		T229	14		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T164	13		T140	1		T155	29
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T206	12		T165	1		T245	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T47	1		T49	4		T222	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T53	1		T156	1		T137	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T48	1		T156	1		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T69	2		T316	1		T99	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T17	1		T317	1		T318	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14620	1			T2	20		T4	13		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T56	12		T146	12		T246	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T250	11		T317	9		T311	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	1		T152	6		T250	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	949	1			T12	21		T141	14		T248	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T270	4		T211	2		T301	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T16	11		T50	1		T137	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T19	8		T138	15		T223	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T18	1		T19	6		T239	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T138	1		T236	9		T166	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T157	16		T231	13		T234	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	3		T138	13		T189	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T228	9		T240	6		T234	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T8	3		T53	5		T152	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T229	12		T239	13		T200	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T164	13		T140	15		T155	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T245	1		T227	1		T267	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T166	15		T247	11		T230	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T53	15		T156	3		T137	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T156	10		T174	12		T153	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T69	1		T99	10		T90	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T317	3		T319	10		T320	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	1		T40	1		T20	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T56	10		T146	9		T246	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T53	1		T156	1		T220	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T156	1		T208	1		T153	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T315	7		T296	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T20	5		T150	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T14	5		T15	8		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1616	1			T12	3		T81	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T220	1		T195	1		T30	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T16	1		T19	1		T50	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	2		T19	1		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T18	3		T137	1		T239	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T54	1		T138	1		T250	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T157	1		T231	1		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T13	5		T52	14		T189	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T234	17		T190	1		T321	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T53	10		T136	9		T138	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T139	13		T222	1		T174	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T8	6		T164	13		T136	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T206	12		T229	14		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T47	1		T49	4		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T137	9		T51	2		T56	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T17	1		T48	1		T222	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14582	1			T2	20		T4	13		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T53	15		T156	3		T220	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T156	10		T153	11		T322	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T315	7		T296	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T20	2		T28	2		T250	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	1		T56	10		T146	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	954	1			T12	21		T141	14		T248	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T250	10		T270	4		T211	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T16	11		T19	6		T50	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T19	8		T138	15		T223	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T18	1		T137	1		T239	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T138	1		T250	13		T236	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T157	16		T231	13		T241	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	3		T189	4		T225	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T234	15		T190	11		T321	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T53	5		T138	13		T152	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T228	9		T240	6		T239	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	3		T164	13		T140	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T229	12		T245	1		T227	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T166	15		T247	11		T230	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T137	18		T56	8		T232	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T174	12		T233	11		T229	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	1		T40	1		T216	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T150	2		T158	1		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	5		T15	1		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T12	24		T81	1		T141	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T220	1		T195	1		T30	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T16	12		T50	4		T137	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	2		T19	9		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T18	3		T19	7		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T138	2		T195	1		T236	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T157	17		T231	14		T234	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T13	4		T52	1		T138	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T139	1		T222	1		T228	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	6		T53	6		T136	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T174	1		T229	13		T239	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T164	14		T140	16		T155	24
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T206	1		T165	1		T245	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T47	1		T49	3		T222	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T53	16		T156	4		T137	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T48	1		T156	11		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T69	3		T316	1		T99	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T17	1		T317	4		T318	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14730	1			T2	20		T3	1		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T56	11		T146	10		T246	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T154	7		T269	15		T311	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	1		T15	7		T136	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T221	2		T135	33		T137	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T270	7		T211	8		T273	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T50	1		T139	12		T188	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T138	14		T223	16		T153	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T18	1		T239	10		T232	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T236	11		T166	12		T246	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T234	2		T241	13		T268	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	4		T52	13		T138	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T139	12		T228	6		T240	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	3		T53	9		T136	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T229	13		T323	1		T200	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T164	12		T155	27		T246	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T206	11		T245	1		T227	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T49	1		T166	17		T247	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T137	8		T56	10		T229	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T144	13		T174	10		T153	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T99	3		T90	17		T324	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T20	2		T28	1		T325	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T56	11		T146	11		T246	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T53	16		T156	4		T220	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T156	11		T208	1		T153	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T315	8		T296	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T20	5		T150	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T14	5		T15	1		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T12	24		T81	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T220	1		T195	1		T30	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T16	12		T19	7		T50	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	2		T19	9		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T18	3		T137	2		T239	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T54	1		T138	2		T250	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T157	17		T231	14		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	4		T52	1		T189	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T234	17		T190	12		T321	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T53	6		T136	1		T138	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T139	1		T222	1		T174	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T8	6		T164	14		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T206	1		T229	13		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T47	1		T49	3		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T137	19		T51	2		T56	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T17	1		T48	1		T222	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14678	1			T2	20		T3	1		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T232	11		T247	10		T260	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T153	11		T258	9		T326	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T315	6		T296	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T20	2		T28	1		T154	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T14	1		T15	7		T136	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T221	2		T135	33		T137	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T253	13		T270	7		T211	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T50	1		T139	12		T188	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T138	14		T223	16		T153	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T18	1		T239	10		T232	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T236	11		T166	12		T246	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T253	6		T241	13		T107	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T13	4		T52	13		T189	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T234	15		T300	12		T243	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T53	9		T136	8		T138	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T139	12		T228	6		T240	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	3		T164	12		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T206	11		T229	13		T245	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T49	1		T166	17		T247	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T137	8		T56	10		T229	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T144	13		T174	10		T229	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

auto[0]

4203

1

T8

3

T13

4

T14

1