Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23659

1

T2

20

T3

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20168

1

T2

20

T3

1

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3491

1

T3

2

T13

8

T16

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17422

1

T2

20

T3

3

T4

13

auto[1]

6237

1

T12

24

T14

10

T40

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19765

1

T2

20

T3

2

T4

13

auto[1]

3894

1

T3

1

T8

3

T12

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	661	1			T14	4		T40	2		T18	2
values[0]	46	1			T28	6		T296	18		T297	22
values[1]	677	1			T54	1		T136	9		T206	12
values[2]	2885	1			T12	24		T19	9		T53	16
values[3]	878	1			T137	41		T225	16		T233	11
values[4]	666	1			T150	1		T49	4		T139	13
values[5]	739	1			T14	6		T18	4		T52	14
values[6]	562	1			T8	9		T15	8		T19	7
values[7]	608	1			T3	2		T16	12		T20	7
values[8]	551	1			T13	8		T139	13		T140	16
values[9]	1052	1			T17	1		T47	1		T150	1
minimum	14334	1			T2	20		T3	1		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	676	1			T54	1		T136	24		T206	12
values[1]	2943	1			T12	24		T19	9		T53	16
values[2]	845	1			T137	41		T152	27		T225	16
values[3]	571	1			T150	1		T49	4		T139	13
values[4]	775	1			T14	6		T15	8		T18	4
values[5]	558	1			T8	9		T16	12		T208	1
values[6]	542	1			T3	2		T20	7		T47	1
values[7]	578	1			T13	8		T139	13		T138	30
values[8]	1187	1			T17	1		T47	1		T48	1
values[9]	88	1			T150	1		T240	11		T224	22
minimum	14896	1			T2	20		T3	1		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

4203

1

T8

3

T13

4

T14

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T136	24		T206	12		T155	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T54	1		T142	1		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1590	1			T12	3		T81	1		T141	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T19	1		T53	1		T234	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T233	1		T195	1		T267	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T137	17		T152	16		T225	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T150	1		T49	4		T139	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T228	7		T231	1		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T14	5		T15	8		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T18	3		T19	1		T52	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	6		T208	1		T146	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T16	1		T220	1		T254	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T20	5		T140	1		T188	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	2		T47	1		T53	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T138	15		T220	1		T253	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T13	5		T139	13		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T156	1		T158	1		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T17	1		T47	1		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T150	1		T240	5		T277	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T224	10		T197	1		T327	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14641	1			T2	20		T4	13		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T227	19		T250	1		T323	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T155	9		T231	6		T239	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T153	11		T245	1		T190	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	966	1			T12	21		T141	14		T164	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T19	8		T53	15		T234	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T233	10		T267	4		T247	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T137	24		T152	11		T225	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T189	4		T226	13		T237	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T228	9		T231	13		T236	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T14	1		T156	10		T221	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T18	1		T19	6		T233	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T8	3		T146	9		T152	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T16	11		T220	7		T254	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T20	2		T140	15		T188	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T53	5		T157	16		T137	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T138	15		T236	9		T249	30
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T13	3		T153	11		T233	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T156	3		T56	8		T174	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T50	1		T56	10		T216	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T240	6		T277	4		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T224	12		T278	6		T293	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	1		T40	1		T28	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T227	1		T250	11		T262	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	420	1			T14	4		T40	2		T18	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T56	12		T232	12		T197	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T28	4		T296	8		T297	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T136	9		T206	12		T155	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T54	1		T142	1		T153	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1601	1			T12	3		T81	1		T141	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T19	1		T53	1		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T233	1		T195	1		T267	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T137	17		T225	9		T234	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T150	1		T49	4		T139	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T152	16		T154	8		T228	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T14	5		T156	1		T138	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T18	3		T52	14		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	6		T15	8		T221	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T19	1		T220	1		T229	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T20	5		T208	1		T146	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	2		T16	1		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T140	1		T138	15		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T13	5		T139	13		T233	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T150	1		T158	1		T56	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T17	1		T47	1		T48	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14238	1			T2	20		T4	13		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T156	3		T107	9		T317	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T56	10		T232	10		T278	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T28	2		T296	10		T297	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T155	9		T231	6		T239	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T153	11		T245	1		T227	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T12	21		T141	14		T164	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T19	8		T53	15		T264	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T233	10		T267	4		T247	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T137	24		T225	7		T234	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T189	4		T226	13		T237	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T152	11		T228	9		T231	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	1		T156	10		T138	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T18	1		T233	2		T224	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T8	3		T221	2		T188	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T19	6		T220	7		T229	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T20	2		T146	9		T328	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T16	11		T53	5		T157	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T140	15		T138	15		T236	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T13	3		T233	11		T97	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T56	8		T174	12		T229	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T50	1		T216	1		T153	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	1		T40	1		T216	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T136	2		T206	1		T155	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T54	1		T142	1		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T12	24		T81	1		T141	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T19	9		T53	16		T234	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T233	11		T195	1		T267	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T137	26		T152	12		T225	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T150	1		T49	3		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T228	10		T231	14		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T14	5		T15	1		T156	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T18	3		T19	7		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T8	6		T208	1		T146	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T16	12		T220	8		T254	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T20	5		T140	16		T188	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	2		T47	1		T53	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T138	16		T220	1		T253	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T13	4		T139	1		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T156	4		T158	1		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T17	1		T47	1		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T150	1		T240	7		T277	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T224	13		T197	1		T327	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14750	1			T2	20		T3	1		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T227	2		T250	12		T323	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T136	22		T206	11		T155	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T153	11		T245	1		T241	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T164	12		T135	33		T252	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T234	2		T260	2		T316	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T267	4		T247	9		T280	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T137	15		T152	15		T225	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T49	1		T139	12		T189	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T228	6		T236	5		T329	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	1		T15	7		T221	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T18	1		T52	13		T229	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	3		T146	11		T152	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T254	1		T166	12		T268	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T20	2		T188	8		T247	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T53	9		T270	7		T107	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T138	14		T253	13		T236	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T13	4		T139	12		T153	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T56	10		T174	10		T229	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T50	1		T56	11		T229	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T240	4		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T224	9		T278	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T28	1		T305	1		T330	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T227	18		T323	14		T262	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	423	1			T14	4		T40	2		T18	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T56	11		T232	11		T197	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T28	5		T296	11		T297	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T136	1		T206	1		T155	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T54	1		T142	1		T153	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T12	24		T81	1		T141	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T19	9		T53	16		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T233	11		T195	1		T267	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T137	26		T225	8		T234	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T150	1		T49	3		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T152	12		T154	1		T228	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T14	5		T156	11		T138	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T18	3		T52	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	6		T15	1		T221	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T19	7		T220	8		T229	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T20	5		T208	1		T146	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	2		T16	12		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T140	16		T138	16		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T13	4		T139	1		T233	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T150	1		T158	1		T56	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T17	1		T47	1		T48	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14334	1			T2	20		T3	1		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T255	20		T107	4		T281	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T56	11		T232	11		T278	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T28	1		T296	7		T297	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T136	8		T206	11		T155	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T153	11		T245	1		T227	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T164	12		T135	33		T136	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T331	14		T170	10		T299	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T267	4		T247	9		T237	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T137	15		T225	8		T234	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T49	1		T139	12		T189	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T152	15		T154	7		T228	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T14	1		T138	17		T144	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T18	1		T52	13		T256	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	3		T15	7		T221	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T229	13		T166	12		T268	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T20	2		T146	11		T246	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T53	9		T254	1		T270	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T138	14		T253	13		T236	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T13	4		T139	12		T273	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T56	10		T174	10		T229	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T50	1		T153	11		T229	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19456

1

T2

20

T3

3

T4

13

auto[1]

auto[0]

4203

1

T8

3

T13

4

T14

1