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 LINE       60
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       72
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T23,T25
1	0	Covered	T66,T67,T68

 LINE       79
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T21,T23,T25
0	1	0	Covered	T66,T67,T68
1	0	0	Covered	T21,T23,T25

 LINE       121
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T66,T67,T68
0	1	0	Covered	T69,T70,T71
1	0	0	Excluded		VC_COV_UNR

 LINE       3977
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_INTR_STATE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       3978
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_INTR_ENABLE_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       3979
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_INTR_TEST_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       3980
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ALERT_TEST_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       3981
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_EN_CTL_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3982
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_PD_CTL_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       3983
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_LP_SAMPLE_CTL_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       3984
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_SAMPLE_CTL_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       3985
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_FSM_RST_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       3986
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       3987
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       3988
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_2_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       3989
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_3_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       3990
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_4_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       3991
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_5_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       3992
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_6_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       3993
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_7_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       3994
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       3995
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       3996
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_2_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       3997
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_3_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       3998
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_4_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       3999
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_5_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       4000
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_6_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       4001
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_7_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       4002
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN_VAL_0_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T6

 LINE       4003
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN_VAL_1_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       4004
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_WAKEUP_CTL_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       4005
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_FILTER_STATUS_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       4006
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_INTR_CTL_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       4007
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_INTR_STATUS_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T6

 LINE       4008
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_FSM_STATE_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T8

 LINE       4011
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       4011
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5

 LINE       4015
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[28] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T69,T70,T71

 LINE       4015
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b0011 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b0011 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
32 (addr_hit[31] & ((\|(4'...	Covered	T3,T5,T8
31 (addr_hit[30] & ((\|(4'...	Covered	T3,T5,T6
30 (addr_hit[29] & ((\|(4'...	Covered	T1,T5,T8
29 (addr_hit[28] & ((\|(4'...	Covered	T3,T5,T8
28 (addr_hit[27] & ((\|(4'...	Covered	T3,T5,T8
27 (addr_hit[26] & ((\|(4'...	Covered	T1,T3,T5
26 (addr_hit[25] & ((\|(4'...	Covered	T3,T5,T6
25 (addr_hit[24] & ((\|(4'...	Covered	T3,T5,T8
24 (addr_hit[23] & ((\|(4'...	Covered	T3,T5,T8
23 (addr_hit[22] & ((\|(4'...	Covered	T3,T5,T8
22 (addr_hit[21] & ((\|(4'...	Covered	T3,T5,T8
21 (addr_hit[20] & ((\|(4'...	Covered	T3,T5,T8
20 (addr_hit[19] & ((\|(4'...	Covered	T1,T5,T8
19 (addr_hit[18] & ((\|(4'...	Covered	T3,T5,T8
18 (addr_hit[17] & ((\|(4'...	Covered	T3,T5,T8
17 (addr_hit[16] & ((\|(4'...	Covered	T3,T5,T8
16 (addr_hit[15] & ((\|(4'...	Covered	T3,T5,T8
15 (addr_hit[14] & ((\|(4'...	Covered	T3,T5,T8
14 (addr_hit[13] & ((\|(4'...	Covered	T1,T3,T5
13 (addr_hit[12] & ((\|(4'...	Covered	T3,T5,T8
12 (addr_hit[11] & ((\|(4'...	Covered	T3,T5,T8
11 (addr_hit[10] & ((\|(4'...	Covered	T3,T5,T8
10 (addr_hit[9] & ((\|(4'b...	Covered	T3,T5,T8
9 (addr_hit[8] & ((\|(4'b...	Covered	T3,T5,T8
8 (addr_hit[7] & ((\|(4'b...	Covered	T3,T5,T8
7 (addr_hit[6] & ((\|(4'b...	Covered	T3,T5,T8
6 (addr_hit[5] & ((\|(4'b...	Covered	T3,T5,T8
5 (addr_hit[4] & ((\|(4'b...	Covered	T3,T5,T8
4 (addr_hit[3] & ((\|(4'b...	Covered	T3,T5,T8
3 (addr_hit[2] & ((\|(4'b...	Covered	T3,T11,T14
2 (addr_hit[1] & ((\|(4'b...	Covered	T3,T5,T8
1 (addr_hit[0] & ((\|(4'b...	Covered	T1,T3,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T3,T5,T8
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T3,T5,T8
1	1	Covered	T3,T11,T14

 LINE       4015
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T21
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T3,T5,T8
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T8
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T12
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T12
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T25
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T8
1	1	Covered	T1,T3,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T12
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T12
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T8
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T12
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T12
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T12
1	1	Covered	T1,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T10
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T12
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T12
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T12
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T12
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       4015
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T3,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T8
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T8
1	1	Covered	T3,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T5,T8

 LINE       4015
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       4015
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T3,T5,T8
1	1	Covered	T3,T5,T8

 LINE       4051
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T5,T8
1	1	0	Covered	T72,T73,T74
1	1	1	Covered	T3,T8,T11

 LINE       4054
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T5,T8
1	1	0	Covered	T72,T74,T75
1	1	1	Covered	T3,T11,T40

 LINE       4057
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T72,T73,T74
1	1	1	Covered	T1,T22,T24

 LINE       4060
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T74,T75,T76
1	1	1	Covered	T2,T3,T4

 LINE       4063
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T72,T73,T74
1	1	1	Covered	T2,T3,T4

 LINE       4067
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T72,T73,T74
1	1	1	Covered	T1,T3,T21

 LINE       4069
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T73,T74,T75
1	1	1	Covered	T1,T3,T21

 LINE       4071
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T5,T8
1	1	0	Covered	T75,T76,T77
1	1	1	Covered	T12,T13,T14

 LINE       4073
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T5,T8
1	1	0	Covered	T72,T74,T76
1	1	1	Covered	T3,T8,T12

 LINE       4078
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T5,T8
1	1	0	Covered	T72,T73,T74
1	1	1	Covered	T3,T8,T12

 LINE       4083
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T5,T8
1	1	0	Covered	T70,T72,T74
1	1	1	Covered	T3,T8,T12

 LINE       4088
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T5,T8
1	1	0	Covered	T73,T74,T75
1	1	1	Covered	T3,T8,T12

 LINE       4093
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T72,T73,T74
1	1	1	Covered	T3,T8,T12

 LINE       4098
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T5,T8
1	1	0	Covered	T74,T76,T77
1	1	1	Covered	T3,T8,T12

 LINE       4103
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T5,T8
1	1	0	Covered	T73,T74,T76
1	1	1	Covered	T3,T8,T12

 LINE       4108
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T74,T76,T77
1	1	1	Covered	T3,T8,T12

 LINE       4113
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T5,T8
1	1	0	Covered	T72,T73,T74
1	1	1	Covered	T3,T8,T12

 LINE       4118
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T5,T8
1	1	0	Covered	T73,T75,T78
1	1	1	Covered	T3,T8,T12

 LINE       4123
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T72,T73,T74
1	1	1	Covered	T3,T8,T12

 LINE       4128
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T5,T8
1	1	0	Covered	T72,T73,T74
1	1	1	Covered	T3,T8,T12

 LINE       4133
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T5,T8
1	1	0	Covered	T72,T73,T74
1	1	1	Covered	T3,T8,T12

 LINE       4138
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T5,T8
1	1	0	Covered	T73,T76,T67
1	1	1	Covered	T3,T8,T12