Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

---

Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5176	1			T2	20		T3	4		T4	20
testmodes[AdcCtrlTestmodeNormal]	4486	1			T3	10		T5	2		T8	8
testmodes[AdcCtrlTestmodeLowpower]	4801	1			T5	4		T6	13		T9	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2602	1			T2	19		T3	1		T4	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1362	1			T3	2		T8	4		T11	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1095	1			T19	1		T48	16		T49	10
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1372	1			T3	3		T8	4		T11	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1613	1			T3	7		T5	1		T8	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1172	1			T5	1		T12	1		T46	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1099	1			T19	1		T48	18		T49	11
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1158	1			T5	1		T9	1		T13	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2290	1			T5	2		T6	12		T9	1