Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.71 99.07 96.67 100.00 100.00 98.83 98.33 91.09


Total tests in report: 920
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
75.15 75.15 97.47 97.47 82.75 82.75 95.73 95.73 54.05 54.05 95.98 95.98 86.48 86.48 13.55 13.55 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2052444428
80.33 5.19 98.46 0.99 87.77 5.02 97.16 1.42 72.97 18.92 97.78 1.79 89.15 2.67 19.04 5.49 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.412456696
83.22 2.89 98.46 0.00 87.81 0.04 97.16 0.00 91.89 18.92 97.84 0.06 89.15 0.00 20.24 1.20 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.713286462
85.91 2.69 98.83 0.37 88.93 1.11 97.16 0.00 97.30 5.41 98.33 0.49 89.48 0.33 31.35 11.11 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.4139502001
87.39 1.48 98.83 0.00 93.91 4.98 97.16 0.00 97.30 0.00 98.45 0.12 89.82 0.33 36.26 4.92 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.379148469
88.53 1.14 98.83 0.00 93.91 0.00 97.16 0.00 97.30 0.00 98.45 0.00 94.49 4.67 39.56 3.29 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3432239133
89.48 0.95 98.83 0.00 93.95 0.04 97.16 0.00 97.30 0.00 98.45 0.00 94.49 0.00 46.17 6.61 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.1804611590
90.30 0.83 98.83 0.00 93.95 0.00 97.16 0.00 97.30 0.00 98.45 0.00 94.66 0.17 51.78 5.62 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.1847840448
90.92 0.62 98.83 0.00 93.95 0.00 97.16 0.00 97.30 0.00 98.45 0.00 94.66 0.00 56.10 4.32 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.4214842369
91.47 0.55 98.83 0.00 93.95 0.00 97.16 0.00 97.30 0.00 98.45 0.00 94.82 0.17 59.80 3.69 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.3155235606
91.93 0.46 98.83 0.00 93.95 0.00 97.16 0.00 97.30 0.00 98.45 0.00 94.82 0.00 62.99 3.19 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.242574096
92.38 0.45 98.83 0.00 95.27 1.32 97.63 0.47 97.30 0.00 98.52 0.06 95.49 0.67 63.64 0.65 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.846495827
92.83 0.45 98.89 0.06 95.39 0.12 99.76 2.13 97.30 0.00 98.70 0.19 95.99 0.50 63.76 0.12 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.4075246399
93.26 0.43 98.92 0.03 95.39 0.00 99.76 0.00 97.30 0.00 98.70 0.00 96.16 0.17 66.56 2.80 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.3733198291
93.65 0.40 98.92 0.00 95.39 0.00 99.76 0.00 100.00 2.70 98.70 0.00 96.16 0.00 66.63 0.07 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_fsm_reset.1114294234
94.01 0.36 98.92 0.00 95.39 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.33 0.17 68.95 2.32 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.371489376
94.33 0.32 98.92 0.00 95.64 0.25 99.76 0.00 100.00 0.00 98.70 0.00 96.33 0.00 70.95 2.00 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2927373874
94.62 0.30 98.92 0.00 95.64 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.33 0.00 73.02 2.07 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.1113136773
94.90 0.27 98.92 0.00 95.64 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.33 0.00 74.94 1.92 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.1084885589
95.14 0.24 98.92 0.00 95.64 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.33 0.00 76.62 1.67 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.3728231969
95.36 0.22 98.92 0.00 95.64 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.33 0.00 78.19 1.57 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.242159448
95.57 0.21 98.92 0.00 95.64 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.33 0.00 79.64 1.45 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.721901667
95.76 0.19 98.92 0.00 95.64 0.00 99.76 0.00 100.00 0.00 98.70 0.00 97.66 1.34 79.64 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2905463464
95.91 0.15 98.92 0.00 95.64 0.00 99.76 0.00 100.00 0.00 98.70 0.00 97.83 0.17 80.53 0.90 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_clock_gating.4029084465
96.05 0.14 98.92 0.00 95.64 0.00 99.76 0.00 100.00 0.00 98.70 0.00 98.00 0.17 81.33 0.80 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.3325546555
96.16 0.11 98.92 0.00 95.64 0.00 99.76 0.00 100.00 0.00 98.70 0.00 98.00 0.00 82.11 0.77 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_clock_gating.1415176537
96.26 0.10 98.92 0.00 95.64 0.00 99.76 0.00 100.00 0.00 98.70 0.00 98.16 0.17 82.63 0.52 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.2730897290
96.35 0.09 98.92 0.00 95.64 0.00 99.76 0.00 100.00 0.00 98.70 0.00 98.16 0.00 83.28 0.65 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_both.310212019
96.44 0.09 98.92 0.00 95.64 0.00 99.76 0.00 100.00 0.00 98.70 0.00 98.16 0.00 83.90 0.62 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.1815042427
96.52 0.08 98.92 0.00 95.64 0.00 99.76 0.00 100.00 0.00 98.70 0.00 98.16 0.00 84.48 0.57 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.4061563597
96.60 0.07 98.92 0.00 95.64 0.00 99.76 0.00 100.00 0.00 98.70 0.00 98.16 0.00 85.00 0.52 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.2384250728
96.67 0.07 98.92 0.00 95.92 0.29 99.76 0.00 100.00 0.00 98.70 0.00 98.16 0.00 85.20 0.20 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1227682139
96.73 0.06 99.01 0.09 96.05 0.12 100.00 0.24 100.00 0.00 98.70 0.00 98.16 0.00 85.20 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.2223807139
96.79 0.06 99.07 0.06 96.29 0.25 100.00 0.00 100.00 0.00 98.83 0.12 98.16 0.00 85.20 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1003748988
96.85 0.06 99.07 0.00 96.29 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.00 85.63 0.42 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_clock_gating.4232748492
96.91 0.06 99.07 0.00 96.29 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.17 85.87 0.25 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.900590595
96.97 0.05 99.07 0.00 96.29 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 86.25 0.37 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3320314165
97.02 0.05 99.07 0.00 96.29 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 86.62 0.37 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.412572335
97.07 0.05 99.07 0.00 96.29 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 86.95 0.32 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.2590557393
97.11 0.05 99.07 0.00 96.29 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 87.27 0.32 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup.129734758
97.15 0.04 99.07 0.00 96.54 0.25 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 87.30 0.02 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.4055982431
97.19 0.04 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 87.55 0.25 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_both.3575788464
97.22 0.03 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 87.77 0.22 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.1765870642
97.25 0.03 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.00 0.22 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_both.3173041206
97.28 0.03 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.22 0.22 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_clock_gating.1689955570
97.31 0.03 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.42 0.20 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.623281760
97.34 0.03 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.62 0.20 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt.1670612608
97.36 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.77 0.15 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3345056921
97.38 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 88.92 0.15 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_both.1376329855
97.41 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.07 0.15 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all.3594553737
97.42 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.19 0.12 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.2668301154
97.44 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.32 0.12 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.1462027211
97.46 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.44 0.12 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all.1386575964
97.48 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.57 0.12 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup.284100444
97.50 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.69 0.12 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1183952822
97.51 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.82 0.12 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.2649482299
97.53 0.02 99.07 0.00 96.67 0.12 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.82 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2988666129
97.54 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.92 0.10 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.2729042061
97.56 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.02 0.10 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.969551224
97.57 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.12 0.10 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.3438283360
97.59 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.22 0.10 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.466857724
97.60 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.29 0.07 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.2787370325
97.61 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.37 0.07 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.1921181769
97.62 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.44 0.07 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt.153743362
97.63 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.49 0.05 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.1978303818
97.63 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.54 0.05 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.4208222630
97.64 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.59 0.05 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1218956571
97.65 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.64 0.05 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.200863538
97.66 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.69 0.05 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.4140505610
97.66 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.74 0.05 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all.149135313
97.67 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.77 0.02 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2108369376
97.67 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.79 0.02 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.809130330
97.67 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.82 0.02 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.2973254252
97.68 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.84 0.02 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.2611819789
97.68 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.87 0.02 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_both.3178847763
97.68 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.89 0.02 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all.108511420
97.69 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.92 0.02 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.443407166
97.69 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.94 0.02 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.1038497367
97.69 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.97 0.02 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup.2341134249
97.70 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.99 0.02 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.30012267
97.70 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.02 0.02 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_fsm_reset.1252952133
97.71 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.04 0.02 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup.3793850160
97.71 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.07 0.02 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3104254577
97.71 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.09 0.02 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1642301153

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2771619515
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3673040612
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2427742278
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1631994785
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3631520354
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.2417476332
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2809419815
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1139831533
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2249299931
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1160918721
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4250362991
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3937249592
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.1431870029
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2284767619
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3325220674
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3147757375
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4260596108
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.179376893
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2555946498
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.106452942
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.275740424
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2182274248
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.1921991171
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3694704227
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1328005588
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2804610307
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2099336498
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2197446884
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.3566345161
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1110956375
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1662930977
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3248991993
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3773303032
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1413493458
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.2524666903
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2876669698
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.4254739197
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3117456906
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1962404528
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.1780080225
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3892298991
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2660045786
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3265061355
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.281990808
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1263256018
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.877719423
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1462179229
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1207574311
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1518136596
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3922851909
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.766240013
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.4100232617
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1190142506
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2683519472
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3576448959
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3536811872
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2016752137
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.1665503668
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4284759848
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3185008403
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3159372513
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3097339510
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2245357777
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.1718292756
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.926267961
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1940866533
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3428202047
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3901058622
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3503979132
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.1010764018
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3888894877
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2498399460
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.516652359
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4207360036
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1598660051
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1174886651
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2154198445
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1831717786
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.2025502524
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2725373979
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3630829104
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1861575837
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.2682347542
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.1443044108
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.4215420479
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.1777850830
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.3708577075
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.2607729583
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.4045604102
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.2856919602
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.3239330671
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.2208327500
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.246269338
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2395101696
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2429368533
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2594171600
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3654559794
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.2092764388
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3855258083
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3737957959
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.686502832
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.1238047299
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.1127762045
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.3917812299
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.1445633494
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.1480731718
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.883856270
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.2664882294
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.2554881185
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.2944039465
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.728903590
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1379179521
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.823363266
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3421587525
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3732848435
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.3159126182
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4125965902
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.286479505
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3648763563
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.227055072
/workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.1282809056
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Total test records in report: 920
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.2223807139 Sep 01 07:37:41 AM UTC 24 Sep 01 07:37:44 AM UTC 24 452731845 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.2042742267 Sep 01 07:37:39 AM UTC 24 Sep 01 07:37:47 AM UTC 24 6041123954 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.3029991871 Sep 01 07:37:41 AM UTC 24 Sep 01 07:37:48 AM UTC 24 3871506609 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.3465871094 Sep 01 07:37:41 AM UTC 24 Sep 01 07:37:48 AM UTC 24 5871447344 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.4075246399 Sep 01 07:37:41 AM UTC 24 Sep 01 07:37:53 AM UTC 24 7720108714 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.1475926118 Sep 01 07:37:54 AM UTC 24 Sep 01 07:37:56 AM UTC 24 443755081 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.1382883205 Sep 01 07:37:49 AM UTC 24 Sep 01 07:37:58 AM UTC 24 7769609763 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2052444428 Sep 01 07:37:41 AM UTC 24 Sep 01 07:38:01 AM UTC 24 12079796659 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.4213034562 Sep 01 07:37:41 AM UTC 24 Sep 01 07:38:02 AM UTC 24 29754536217 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.431025642 Sep 01 07:37:57 AM UTC 24 Sep 01 07:38:03 AM UTC 24 5967211445 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.4031530849 Sep 01 07:37:44 AM UTC 24 Sep 01 07:38:09 AM UTC 24 4306919763 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1552597285 Sep 01 07:37:49 AM UTC 24 Sep 01 07:38:13 AM UTC 24 4080665849 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.183311497 Sep 01 07:37:46 AM UTC 24 Sep 01 07:38:19 AM UTC 24 45666139310 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.3472164945 Sep 01 07:38:20 AM UTC 24 Sep 01 07:38:37 AM UTC 24 3580148583 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.412456696 Sep 01 07:37:49 AM UTC 24 Sep 01 07:38:44 AM UTC 24 197776841953 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.4055982431 Sep 01 07:38:37 AM UTC 24 Sep 01 07:38:52 AM UTC 24 7405826111 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.643720665 Sep 01 07:38:44 AM UTC 24 Sep 01 07:38:53 AM UTC 24 3831540927 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.2720810958 Sep 01 07:38:53 AM UTC 24 Sep 01 07:38:57 AM UTC 24 417970778 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.3852041628 Sep 01 07:38:09 AM UTC 24 Sep 01 07:38:57 AM UTC 24 182562003369 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.464724190 Sep 01 07:38:54 AM UTC 24 Sep 01 07:38:59 AM UTC 24 5883164053 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.379148469 Sep 01 07:37:43 AM UTC 24 Sep 01 07:39:31 AM UTC 24 328675909940 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.900590595 Sep 01 07:37:43 AM UTC 24 Sep 01 07:39:46 AM UTC 24 168809346221 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.2261426567 Sep 01 07:37:43 AM UTC 24 Sep 01 07:39:55 AM UTC 24 174831201474 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.3201907777 Sep 01 07:39:56 AM UTC 24 Sep 01 07:40:07 AM UTC 24 3943578112 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.2905448673 Sep 01 07:38:30 AM UTC 24 Sep 01 07:40:09 AM UTC 24 21137551467 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.869225890 Sep 01 07:37:43 AM UTC 24 Sep 01 07:40:13 AM UTC 24 405581893654 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2664861602 Sep 01 07:40:15 AM UTC 24 Sep 01 07:40:31 AM UTC 24 8334139813 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.4158750410 Sep 01 07:40:07 AM UTC 24 Sep 01 07:40:46 AM UTC 24 34442975501 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.247368442 Sep 01 07:40:47 AM UTC 24 Sep 01 07:40:49 AM UTC 24 482692798 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.2260536165 Sep 01 07:40:49 AM UTC 24 Sep 01 07:40:58 AM UTC 24 5951816245 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.1655162064 Sep 01 07:40:42 AM UTC 24 Sep 01 07:41:13 AM UTC 24 7707085737 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3320314165 Sep 01 07:37:39 AM UTC 24 Sep 01 07:41:34 AM UTC 24 325256473125 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.3965301491 Sep 01 07:38:02 AM UTC 24 Sep 01 07:42:35 AM UTC 24 327506353156 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3264628015 Sep 01 07:38:04 AM UTC 24 Sep 01 07:42:40 AM UTC 24 325965997864 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.3781998607 Sep 01 07:42:41 AM UTC 24 Sep 01 07:42:45 AM UTC 24 3950805976 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2927373874 Sep 01 07:37:41 AM UTC 24 Sep 01 07:42:57 AM UTC 24 196393293645 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.3206655097 Sep 01 07:37:59 AM UTC 24 Sep 01 07:43:12 AM UTC 24 160898740182 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.4195616227 Sep 01 07:42:59 AM UTC 24 Sep 01 07:43:14 AM UTC 24 20012272503 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.1210997094 Sep 01 07:37:41 AM UTC 24 Sep 01 07:43:17 AM UTC 24 435358754202 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.2429132187 Sep 01 07:43:15 AM UTC 24 Sep 01 07:43:19 AM UTC 24 477059542 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.818728869 Sep 01 07:43:17 AM UTC 24 Sep 01 07:43:25 AM UTC 24 5689227244 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.209457853 Sep 01 07:39:00 AM UTC 24 Sep 01 07:43:42 AM UTC 24 328625957788 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.972443479 Sep 01 07:43:13 AM UTC 24 Sep 01 07:43:46 AM UTC 24 8183450889 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.1474839060 Sep 01 07:42:36 AM UTC 24 Sep 01 07:43:56 AM UTC 24 174101192864 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.705217509 Sep 01 07:39:34 AM UTC 24 Sep 01 07:44:13 AM UTC 24 353463388185 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.952122630 Sep 01 07:39:03 AM UTC 24 Sep 01 07:44:41 AM UTC 24 163412620895 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.319133709 Sep 01 07:42:46 AM UTC 24 Sep 01 07:44:42 AM UTC 24 29916656247 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.3819977508 Sep 01 07:44:40 AM UTC 24 Sep 01 07:44:55 AM UTC 24 4499077290 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.1097587695 Sep 01 07:40:59 AM UTC 24 Sep 01 07:45:07 AM UTC 24 328876488767 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.3733198291 Sep 01 07:38:04 AM UTC 24 Sep 01 07:45:08 AM UTC 24 558634224524 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.3477494377 Sep 01 07:45:08 AM UTC 24 Sep 01 07:45:11 AM UTC 24 297225263 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.1254070190 Sep 01 07:37:39 AM UTC 24 Sep 01 07:45:12 AM UTC 24 166112557330 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1904331140 Sep 01 07:44:55 AM UTC 24 Sep 01 07:45:13 AM UTC 24 2898446737 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.2164443413 Sep 01 07:45:09 AM UTC 24 Sep 01 07:45:18 AM UTC 24 6032383955 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.2855246962 Sep 01 07:37:41 AM UTC 24 Sep 01 07:45:37 AM UTC 24 78172189417 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.371489376 Sep 01 07:38:03 AM UTC 24 Sep 01 07:45:39 AM UTC 24 487058446087 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.4061563597 Sep 01 07:37:39 AM UTC 24 Sep 01 07:45:39 AM UTC 24 167270536613 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.1900252478 Sep 01 07:44:42 AM UTC 24 Sep 01 07:45:45 AM UTC 24 37776857940 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.535353026 Sep 01 07:45:46 AM UTC 24 Sep 01 07:46:02 AM UTC 24 2984094514 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.443407166 Sep 01 07:40:10 AM UTC 24 Sep 01 07:46:02 AM UTC 24 69749909430 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.1900952853 Sep 01 07:45:07 AM UTC 24 Sep 01 07:46:10 AM UTC 24 79988827905 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.140937479 Sep 01 07:46:27 AM UTC 24 Sep 01 07:46:30 AM UTC 24 289011808 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.3430166995 Sep 01 07:46:31 AM UTC 24 Sep 01 07:46:40 AM UTC 24 5792869693 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.2025826691 Sep 01 07:37:39 AM UTC 24 Sep 01 07:46:42 AM UTC 24 500079179812 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2391865230 Sep 01 07:46:03 AM UTC 24 Sep 01 07:46:42 AM UTC 24 16991110925 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.2271083211 Sep 01 07:45:52 AM UTC 24 Sep 01 07:46:45 AM UTC 24 23612727297 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.3164327523 Sep 01 07:46:12 AM UTC 24 Sep 01 07:46:49 AM UTC 24 32483254864 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.4139502001 Sep 01 07:37:43 AM UTC 24 Sep 01 07:46:55 AM UTC 24 592355427702 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2465352119 Sep 01 07:41:14 AM UTC 24 Sep 01 07:46:57 AM UTC 24 328423604376 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.993063403 Sep 01 07:45:12 AM UTC 24 Sep 01 07:47:04 AM UTC 24 167191735249 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.2927479630 Sep 01 07:37:39 AM UTC 24 Sep 01 07:47:08 AM UTC 24 190739251388 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.769212570 Sep 01 07:45:39 AM UTC 24 Sep 01 07:47:13 AM UTC 24 191735091271 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.1353327719 Sep 01 07:38:37 AM UTC 24 Sep 01 07:47:18 AM UTC 24 174377185125 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.2649482299 Sep 01 07:41:35 AM UTC 24 Sep 01 07:47:19 AM UTC 24 459112400864 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.3406576960 Sep 01 07:47:06 AM UTC 24 Sep 01 07:47:22 AM UTC 24 3156369841 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.4029884200 Sep 01 07:45:14 AM UTC 24 Sep 01 07:47:22 AM UTC 24 161809173865 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.1510884563 Sep 01 07:47:21 AM UTC 24 Sep 01 07:47:25 AM UTC 24 516975641 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.2121943334 Sep 01 07:47:22 AM UTC 24 Sep 01 07:47:32 AM UTC 24 5594368768 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.3204932337 Sep 01 07:47:09 AM UTC 24 Sep 01 07:47:35 AM UTC 24 36339349720 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.233797471 Sep 01 07:47:19 AM UTC 24 Sep 01 07:47:50 AM UTC 24 19228177936 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.591965849 Sep 01 07:38:06 AM UTC 24 Sep 01 07:48:00 AM UTC 24 210840828289 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.1196505985 Sep 01 07:43:00 AM UTC 24 Sep 01 07:48:03 AM UTC 24 327019995832 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.1765870642 Sep 01 07:37:41 AM UTC 24 Sep 01 07:48:23 AM UTC 24 162405901039 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.3938930073 Sep 01 07:37:47 AM UTC 24 Sep 01 07:48:25 AM UTC 24 94386993616 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.4203833433 Sep 01 07:39:10 AM UTC 24 Sep 01 07:48:27 AM UTC 24 178101844627 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.1774825979 Sep 01 07:48:24 AM UTC 24 Sep 01 07:48:30 AM UTC 24 3117170994 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3455598690 Sep 01 07:48:31 AM UTC 24 Sep 01 07:48:47 AM UTC 24 3214956311 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.1034048919 Sep 01 07:48:01 AM UTC 24 Sep 01 07:48:52 AM UTC 24 189379772648 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.1721103030 Sep 01 07:48:26 AM UTC 24 Sep 01 07:48:57 AM UTC 24 46250897392 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.1037373557 Sep 01 07:48:53 AM UTC 24 Sep 01 07:48:57 AM UTC 24 495690517 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.677699781 Sep 01 07:48:57 AM UTC 24 Sep 01 07:49:07 AM UTC 24 5569066742 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.1836086793 Sep 01 07:43:47 AM UTC 24 Sep 01 07:49:35 AM UTC 24 161577160083 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2824218135 Sep 01 07:45:19 AM UTC 24 Sep 01 07:49:42 AM UTC 24 162599838883 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2513712790 Sep 01 07:46:46 AM UTC 24 Sep 01 07:50:06 AM UTC 24 162815579138 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.913779584 Sep 01 07:45:13 AM UTC 24 Sep 01 07:50:29 AM UTC 24 330424169320 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.4289049879 Sep 01 07:46:50 AM UTC 24 Sep 01 07:50:56 AM UTC 24 171280436984 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.2728989361 Sep 01 07:51:31 AM UTC 24 Sep 01 07:51:34 AM UTC 24 2969133389 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.279985462 Sep 01 07:49:42 AM UTC 24 Sep 01 07:51:34 AM UTC 24 167553771292 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.713286462 Sep 01 07:38:33 AM UTC 24 Sep 01 07:51:39 AM UTC 24 105548066984 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.3356154791 Sep 01 07:46:43 AM UTC 24 Sep 01 07:51:54 AM UTC 24 163906249933 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.1737799789 Sep 01 07:51:35 AM UTC 24 Sep 01 07:52:01 AM UTC 24 26212184393 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.3324081022 Sep 01 07:52:02 AM UTC 24 Sep 01 07:52:04 AM UTC 24 320976725 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.2564734169 Sep 01 07:52:05 AM UTC 24 Sep 01 07:52:13 AM UTC 24 5894583727 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3432239133 Sep 01 07:51:40 AM UTC 24 Sep 01 07:52:22 AM UTC 24 20219015660 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3464495842 Sep 01 07:41:38 AM UTC 24 Sep 01 07:52:22 AM UTC 24 597134304288 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.2367271574 Sep 01 07:46:43 AM UTC 24 Sep 01 07:52:27 AM UTC 24 162739460140 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1525685546 Sep 01 07:50:07 AM UTC 24 Sep 01 07:52:28 AM UTC 24 588605452625 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.1327788113 Sep 01 07:43:19 AM UTC 24 Sep 01 07:52:41 AM UTC 24 327681458950 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.2291108915 Sep 01 07:48:28 AM UTC 24 Sep 01 07:52:47 AM UTC 24 76051731987 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.2385848613 Sep 01 07:52:48 AM UTC 24 Sep 01 07:53:06 AM UTC 24 3908520519 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.4154912642 Sep 01 07:47:36 AM UTC 24 Sep 01 07:53:12 AM UTC 24 184964455709 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.2732351672 Sep 01 07:50:56 AM UTC 24 Sep 01 07:53:22 AM UTC 24 190087900179 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.1539664087 Sep 01 07:44:43 AM UTC 24 Sep 01 07:53:32 AM UTC 24 103269004105 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1147854799 Sep 01 07:53:13 AM UTC 24 Sep 01 07:53:32 AM UTC 24 10390782998 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.466857724 Sep 01 07:47:05 AM UTC 24 Sep 01 07:53:36 AM UTC 24 166199687009 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.2998965863 Sep 01 07:53:32 AM UTC 24 Sep 01 07:53:36 AM UTC 24 520418690 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.1050275869 Sep 01 07:42:47 AM UTC 24 Sep 01 07:53:38 AM UTC 24 127455171313 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.1804611590 Sep 01 07:46:58 AM UTC 24 Sep 01 07:53:58 AM UTC 24 518613819342 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.787399851 Sep 01 07:53:32 AM UTC 24 Sep 01 07:53:59 AM UTC 24 5616797317 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.1583707323 Sep 01 07:52:49 AM UTC 24 Sep 01 07:54:01 AM UTC 24 23825259487 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.253615067 Sep 01 07:44:21 AM UTC 24 Sep 01 07:54:05 AM UTC 24 181842634946 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.1377053573 Sep 01 07:52:22 AM UTC 24 Sep 01 07:54:32 AM UTC 24 157535556895 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.1897614122 Sep 01 07:46:41 AM UTC 24 Sep 01 07:55:15 AM UTC 24 337960403262 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.2169994489 Sep 01 07:47:14 AM UTC 24 Sep 01 07:55:19 AM UTC 24 81355649839 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.3676250388 Sep 01 07:55:16 AM UTC 24 Sep 01 07:55:31 AM UTC 24 5044326795 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3567570184 Sep 01 07:45:39 AM UTC 24 Sep 01 07:55:33 AM UTC 24 191757242227 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.4020325754 Sep 01 07:54:00 AM UTC 24 Sep 01 07:55:49 AM UTC 24 347046428360 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.82756661 Sep 01 07:47:23 AM UTC 24 Sep 01 07:55:53 AM UTC 24 334115949855 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3890656535 Sep 01 07:55:34 AM UTC 24 Sep 01 07:55:55 AM UTC 24 11166445931 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.3630949670 Sep 01 07:55:54 AM UTC 24 Sep 01 07:55:56 AM UTC 24 548585726 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1820944906 Sep 01 07:54:05 AM UTC 24 Sep 01 07:56:04 AM UTC 24 169178772658 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.2528905678 Sep 01 07:43:27 AM UTC 24 Sep 01 07:56:05 AM UTC 24 495110135624 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2739389565 Sep 01 07:53:59 AM UTC 24 Sep 01 07:56:16 AM UTC 24 334202889297 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.789976648 Sep 01 07:55:56 AM UTC 24 Sep 01 07:56:22 AM UTC 24 5803449989 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.2694459992 Sep 01 07:53:36 AM UTC 24 Sep 01 07:56:36 AM UTC 24 163941403204 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1729073526 Sep 01 07:43:57 AM UTC 24 Sep 01 07:57:12 AM UTC 24 202742087823 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.2590557393 Sep 01 07:52:28 AM UTC 24 Sep 01 07:57:15 AM UTC 24 351563320481 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.1400027820 Sep 01 07:47:23 AM UTC 24 Sep 01 07:57:19 AM UTC 24 324179524569 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.2132051802 Sep 01 07:48:58 AM UTC 24 Sep 01 07:57:24 AM UTC 24 163721567487 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.745331718 Sep 01 07:57:13 AM UTC 24 Sep 01 07:57:28 AM UTC 24 3295557918 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3386902456 Sep 01 07:57:25 AM UTC 24 Sep 01 07:57:39 AM UTC 24 1788258214 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.2108715494 Sep 01 07:37:43 AM UTC 24 Sep 01 07:57:40 AM UTC 24 327642937387 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.2970955524 Sep 01 07:57:40 AM UTC 24 Sep 01 07:57:43 AM UTC 24 552396855 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2642561757 Sep 01 07:37:43 AM UTC 24 Sep 01 07:57:44 AM UTC 24 325607257901 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.2330301441 Sep 01 07:53:38 AM UTC 24 Sep 01 07:57:51 AM UTC 24 330913981238 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.2735667212 Sep 01 07:57:41 AM UTC 24 Sep 01 07:57:56 AM UTC 24 5823636587 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1501372177 Sep 01 07:52:30 AM UTC 24 Sep 01 07:58:04 AM UTC 24 415917832170 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.2623502602 Sep 01 07:49:08 AM UTC 24 Sep 01 07:58:28 AM UTC 24 327790748548 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.2043772241 Sep 01 07:55:19 AM UTC 24 Sep 01 07:58:30 AM UTC 24 42908207729 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.3325546555 Sep 01 07:52:23 AM UTC 24 Sep 01 07:58:35 AM UTC 24 496595993060 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.1204487882 Sep 01 07:56:22 AM UTC 24 Sep 01 07:58:58 AM UTC 24 207678696530 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.1334260238 Sep 01 07:57:43 AM UTC 24 Sep 01 07:58:59 AM UTC 24 165298399904 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.3997019618 Sep 01 07:58:59 AM UTC 24 Sep 01 07:59:04 AM UTC 24 3598239096 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.515336205 Sep 01 07:48:48 AM UTC 24 Sep 01 07:59:09 AM UTC 24 190551838734 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.4144100122 Sep 01 07:58:59 AM UTC 24 Sep 01 07:59:22 AM UTC 24 24487480034 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.4130803698 Sep 01 07:59:10 AM UTC 24 Sep 01 07:59:46 AM UTC 24 22303401397 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.209412764 Sep 01 07:45:38 AM UTC 24 Sep 01 07:59:48 AM UTC 24 668409683670 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.397903096 Sep 01 07:59:23 AM UTC 24 Sep 01 07:59:49 AM UTC 24 45281325093 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.988371176 Sep 01 07:59:47 AM UTC 24 Sep 01 07:59:50 AM UTC 24 405752114 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.4224604672 Sep 01 07:57:44 AM UTC 24 Sep 01 07:59:54 AM UTC 24 330331977511 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.4030973701 Sep 01 07:59:49 AM UTC 24 Sep 01 07:59:58 AM UTC 24 6122987640 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.650987358 Sep 01 07:40:50 AM UTC 24 Sep 01 08:00:04 AM UTC 24 503632379792 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1083258927 Sep 01 07:47:52 AM UTC 24 Sep 01 08:00:09 AM UTC 24 408957830186 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.1317148768 Sep 01 07:57:16 AM UTC 24 Sep 01 08:00:09 AM UTC 24 40765543369 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.3071012140 Sep 01 07:41:42 AM UTC 24 Sep 01 08:00:23 AM UTC 24 540927121509 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.2074972647 Sep 01 07:41:13 AM UTC 24 Sep 01 08:00:26 AM UTC 24 327713709990 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.4183626300 Sep 01 08:00:27 AM UTC 24 Sep 01 08:00:33 AM UTC 24 3001851708 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.1141007883 Sep 01 08:00:33 AM UTC 24 Sep 01 08:00:41 AM UTC 24 27867757618 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3443082497 Sep 01 07:54:02 AM UTC 24 Sep 01 08:00:49 AM UTC 24 577260218143 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3125481862 Sep 01 07:43:42 AM UTC 24 Sep 01 08:00:54 AM UTC 24 482839310802 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.2668301154 Sep 01 07:55:51 AM UTC 24 Sep 01 08:00:56 AM UTC 24 218744749030 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.3911222491 Sep 01 08:00:57 AM UTC 24 Sep 01 08:01:00 AM UTC 24 307491716 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.901173124 Sep 01 08:00:50 AM UTC 24 Sep 01 08:01:05 AM UTC 24 6304014807 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.963709807 Sep 01 07:38:58 AM UTC 24 Sep 01 08:01:08 AM UTC 24 492507109707 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.2223316420 Sep 01 08:01:01 AM UTC 24 Sep 01 08:01:23 AM UTC 24 6151301180 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.1508745171 Sep 01 07:47:20 AM UTC 24 Sep 01 08:01:27 AM UTC 24 331576636053 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.873083012 Sep 01 08:00:23 AM UTC 24 Sep 01 08:01:31 AM UTC 24 156570452722 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.1531920091 Sep 01 07:51:55 AM UTC 24 Sep 01 08:01:45 AM UTC 24 332765538763 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.3321454664 Sep 01 07:53:39 AM UTC 24 Sep 01 08:01:45 AM UTC 24 168048456899 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.853761135 Sep 01 07:46:02 AM UTC 24 Sep 01 08:01:55 AM UTC 24 122519520516 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.1535859585 Sep 01 08:01:56 AM UTC 24 Sep 01 08:02:01 AM UTC 24 3875441038 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.1847840448 Sep 01 07:40:32 AM UTC 24 Sep 01 08:02:02 AM UTC 24 608255522491 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.2018658192 Sep 01 07:59:51 AM UTC 24 Sep 01 08:02:05 AM UTC 24 495424131742 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.3155235606 Sep 01 07:37:44 AM UTC 24 Sep 01 08:02:05 AM UTC 24 500620781483 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.724444950 Sep 01 08:02:02 AM UTC 24 Sep 01 08:02:22 AM UTC 24 32114983561 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.1571622266 Sep 01 08:02:23 AM UTC 24 Sep 01 08:02:26 AM UTC 24 500150858 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.13089606 Sep 01 07:56:17 AM UTC 24 Sep 01 08:02:28 AM UTC 24 323258195389 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2041635958 Sep 01 08:01:28 AM UTC 24 Sep 01 08:02:32 AM UTC 24 162181680794 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.809130330 Sep 01 07:52:30 AM UTC 24 Sep 01 08:02:35 AM UTC 24 378371574439 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.4201137454 Sep 01 08:02:06 AM UTC 24 Sep 01 08:02:36 AM UTC 24 13349609828 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.1682572747 Sep 01 07:54:33 AM UTC 24 Sep 01 08:02:53 AM UTC 24 162986127130 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.1384759548 Sep 01 08:02:27 AM UTC 24 Sep 01 08:02:54 AM UTC 24 5803457117 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.3571509643 Sep 01 08:00:09 AM UTC 24 Sep 01 08:03:01 AM UTC 24 610863040857 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.1113136773 Sep 01 07:58:31 AM UTC 24 Sep 01 08:03:06 AM UTC 24 353933199102 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.2608173041 Sep 01 08:01:06 AM UTC 24 Sep 01 08:03:07 AM UTC 24 166705955270 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.3697755002 Sep 01 07:56:05 AM UTC 24 Sep 01 08:03:22 AM UTC 24 319076740387 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.362928573 Sep 01 08:03:07 AM UTC 24 Sep 01 08:03:25 AM UTC 24 3804359556 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.4240280557 Sep 01 08:01:09 AM UTC 24 Sep 01 08:03:50 AM UTC 24 160132928634 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.953395834 Sep 01 08:03:22 AM UTC 24 Sep 01 08:03:50 AM UTC 24 43758761109 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.3649932469 Sep 01 07:59:50 AM UTC 24 Sep 01 08:04:00 AM UTC 24 331197677888 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.1889698546 Sep 01 08:04:00 AM UTC 24 Sep 01 08:04:04 AM UTC 24 333076051 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.2267613348 Sep 01 07:56:06 AM UTC 24 Sep 01 08:04:11 AM UTC 24 161811171746 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.1684258618 Sep 01 08:01:51 AM UTC 24 Sep 01 08:04:12 AM UTC 24 208329639079 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.1815042427 Sep 01 07:58:36 AM UTC 24 Sep 01 08:04:12 AM UTC 24 347601881773 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.4085235620 Sep 01 08:04:05 AM UTC 24 Sep 01 08:04:13 AM UTC 24 5782922726 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.1486689852 Sep 01 07:51:35 AM UTC 24 Sep 01 08:04:15 AM UTC 24 124867766469 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1552057712 Sep 01 08:03:50 AM UTC 24 Sep 01 08:04:26 AM UTC 24 75346526286 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.95250616 Sep 01 07:55:32 AM UTC 24 Sep 01 08:04:29 AM UTC 24 99500661145 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.2980920142 Sep 01 08:04:13 AM UTC 24 Sep 01 08:05:10 AM UTC 24 163578462552 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.3947805357 Sep 01 07:38:14 AM UTC 24 Sep 01 08:05:13 AM UTC 24 504851775493 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.871522974 Sep 01 08:02:36 AM UTC 24 Sep 01 08:05:18 AM UTC 24 161987720486 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.4243688759 Sep 01 07:38:59 AM UTC 24 Sep 01 08:05:20 AM UTC 24 496462376572 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2346941320 Sep 01 07:49:36 AM UTC 24 Sep 01 08:05:26 AM UTC 24 484701394226 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.1229900202 Sep 01 07:57:51 AM UTC 24 Sep 01 08:05:28 AM UTC 24 161549189190 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.2730897290 Sep 01 08:01:46 AM UTC 24 Sep 01 08:05:35 AM UTC 24 516262817416 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.129526056 Sep 01 08:05:13 AM UTC 24 Sep 01 08:05:35 AM UTC 24 4477905458 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2707979370 Sep 01 08:05:28 AM UTC 24 Sep 01 08:05:37 AM UTC 24 3580805663 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.3302023867 Sep 01 08:02:32 AM UTC 24 Sep 01 08:05:38 AM UTC 24 169041970166 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.2172087008 Sep 01 08:05:36 AM UTC 24 Sep 01 08:05:40 AM UTC 24 496566243 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.2909096289 Sep 01 08:05:36 AM UTC 24 Sep 01 08:05:47 AM UTC 24 5598423076 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.3837084870 Sep 01 07:59:55 AM UTC 24 Sep 01 08:05:53 AM UTC 24 166346604991 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.500329619 Sep 01 08:02:38 AM UTC 24 Sep 01 08:06:19 AM UTC 24 486052155774 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.1467157167 Sep 01 07:47:26 AM UTC 24 Sep 01 08:06:23 AM UTC 24 330305699190 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.3438283360 Sep 01 08:03:02 AM UTC 24 Sep 01 08:06:38 AM UTC 24 206865272722 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.4214842369 Sep 01 07:37:41 AM UTC 24 Sep 01 08:06:46 AM UTC 24 687549892594 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.67467297 Sep 01 08:05:19 AM UTC 24 Sep 01 08:06:50 AM UTC 24 43307392292 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.1676112873 Sep 01 08:06:47 AM UTC 24 Sep 01 08:06:53 AM UTC 24 3828633622 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.1834548768 Sep 01 08:05:29 AM UTC 24 Sep 01 08:07:06 AM UTC 24 67905498029 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1863415727 Sep 01 07:58:29 AM UTC 24 Sep 01 08:07:23 AM UTC 24 203127270534 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.4212237337 Sep 01 08:07:07 AM UTC 24 Sep 01 08:07:29 AM UTC 24 9086414967 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.3038413874 Sep 01 08:06:23 AM UTC 24 Sep 01 08:07:33 AM UTC 24 163356908853 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.3316743760 Sep 01 08:07:29 AM UTC 24 Sep 01 08:07:33 AM UTC 24 524201244 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.2302605216 Sep 01 07:50:30 AM UTC 24 Sep 01 08:07:43 AM UTC 24 633201467781 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.1084885589 Sep 01 07:39:46 AM UTC 24 Sep 01 08:07:46 AM UTC 24 540402001941 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.2665604079 Sep 01 08:07:33 AM UTC 24 Sep 01 08:07:53 AM UTC 24 5917882715 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.2973254252 Sep 01 07:57:20 AM UTC 24 Sep 01 08:08:00 AM UTC 24 120044537607 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.561552643 Sep 01 07:59:59 AM UTC 24 Sep 01 08:08:02 AM UTC 24 494018678946 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.3728231969 Sep 01 07:45:40 AM UTC 24 Sep 01 08:08:10 AM UTC 24 520923652978 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.2611819789 Sep 01 08:00:43 AM UTC 24 Sep 01 08:08:28 AM UTC 24 110001756281 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.242159448 Sep 01 08:04:30 AM UTC 24 Sep 01 08:08:34 AM UTC 24 347927084272 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.2729042061 Sep 01 07:53:07 AM UTC 24 Sep 01 08:08:37 AM UTC 24 113246258230 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.2140107085 Sep 01 08:06:51 AM UTC 24 Sep 01 08:08:52 AM UTC 24 36714688923 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.1121607872 Sep 01 08:08:35 AM UTC 24 Sep 01 08:08:56 AM UTC 24 4533213145 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.836386382 Sep 01 08:08:56 AM UTC 24 Sep 01 08:09:03 AM UTC 24 2130789219 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.4061364646 Sep 01 08:08:11 AM UTC 24 Sep 01 08:09:23 AM UTC 24 156785480885 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.741042073 Sep 01 08:09:23 AM UTC 24 Sep 01 08:09:27 AM UTC 24 376694047 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1404685568 Sep 01 08:01:46 AM UTC 24 Sep 01 08:09:27 AM UTC 24 392612473538 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.169887692 Sep 01 08:00:55 AM UTC 24 Sep 01 08:09:30 AM UTC 24 165600828093 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.3127922299 Sep 01 08:04:13 AM UTC 24 Sep 01 08:09:39 AM UTC 24 489752001780 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.14168081 Sep 01 07:39:32 AM UTC 24 Sep 01 08:09:43 AM UTC 24 603835701160 ps
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