Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22473

1

T2

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19004

1

T2

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3469

1

T12

1

T15

13

T16

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16652

1

T2

20

T3

14

T4

20

auto[1]

5821

1

T5

7

T9

1

T13

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18523

1

T2

20

T3

14

T4

20

auto[1]

3950

1

T5

2

T9

2

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T184	1		T221	22		-	-
values[0]	25	1			T222	22		T223	1		T224	1
values[1]	496	1			T225	14		T164	1		T147	1
values[2]	648	1			T5	7		T53	7		T144	1
values[3]	633	1			T129	3		T205	4		T146	41
values[4]	537	1			T46	3		T150	4		T167	6
values[5]	750	1			T12	1		T15	12		T53	10
values[6]	781	1			T13	5		T128	1		T46	5
values[7]	586	1			T17	9		T129	12		T144	1
values[8]	2973	1			T9	1		T18	16		T19	4
values[9]	1420	1			T14	24		T15	13		T16	1
minimum	13601	1			T2	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	750	1			T43	8		T226	10		T225	14
values[1]	561	1			T5	7		T53	7		T144	1
values[2]	685	1			T129	3		T166	32		T131	1
values[3]	538	1			T12	1		T46	3		T150	4
values[4]	857	1			T13	5		T15	12		T46	5
values[5]	702	1			T17	9		T128	1		T152	32
values[6]	2827	1			T9	1		T18	16		T20	17
values[7]	674	1			T19	4		T61	39		T53	8
values[8]	970	1			T14	24		T16	1		T40	6
values[9]	293	1			T15	13		T150	16		T62	19
minimum	13616	1			T2	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

4060

1

T5

1

T13

1

T14

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T226	10		T147	1		T227	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T43	6		T225	8		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T5	5		T53	7		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T205	4		T182	1		T146	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T166	15		T148	9		T228	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T129	1		T131	1		T229	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T46	3		T150	1		T62	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	1		T230	1		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	4		T15	1		T145	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T46	1		T53	10		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T152	18		T205	1		T231	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T17	9		T128	1		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1490	1			T9	1		T18	16		T20	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T175	11		T232	1		T233	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T19	3		T143	11		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T61	21		T53	8		T234	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T14	12		T40	4		T47	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T16	1		T150	1		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T62	9		T131	1		T156	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T15	1		T150	1		T225	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13500	1			T2	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T227	1		T157	2		T235	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T43	2		T225	6		T136	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T5	2		T26	1		T29	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T146	21		T236	2		T237	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T166	17		T148	10		T228	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T129	2		T229	2		T177	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T150	3		T62	1		T27	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T230	13		T196	11		T238	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	1		T15	11		T225	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T46	4		T141	16		T153	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T152	14		T167	11		T239	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T167	7		T198	14		T240	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T20	15		T39	14		T129	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T232	1		T233	6		T241	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T19	1		T143	6		T131	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T61	18		T234	12		T156	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T14	12		T40	2		T47	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T150	12		T142	15		T134	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T62	10		T131	13		T156	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T15	12		T150	15		T225	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	2		T12	1		T13	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T184	1		T221	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T222	6		T224	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T222	16		T223	1		T242	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T227	1		T157	10		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T225	8		T164	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	5		T53	7		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T43	6		T182	1		T237	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T166	15		T244	11		T245	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T129	1		T205	4		T146	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T46	3		T150	1		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T229	9		T246	1		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T15	1		T62	2		T152	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	1		T53	10		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T13	4		T205	1		T231	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T128	1		T46	1		T153	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T129	1		T144	1		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T17	9		T175	11		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1549	1			T9	1		T18	16		T19	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T61	6		T234	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	424	1			T14	12		T40	4		T47	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T15	1		T16	1		T61	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13485	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T221	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T227	1		T157	2		T198	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T225	6		T136	12		T248	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	2		T26	1		T29	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T43	2		T237	15		T197	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T166	17		T180	6		T249	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T129	2		T146	21		T177	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T150	3		T167	5		T246	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T229	2		T196	20		T159	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T15	11		T62	1		T152	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T141	16		T230	13		T94	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	1		T225	1		T167	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T46	4		T153	11		T98	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T129	11		T250	11		T156	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T232	1		T167	7		T156	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1106	1			T19	1		T20	15		T39	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T61	5		T234	12		T149	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T14	12		T40	2		T47	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T15	12		T61	13		T150	27
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	2		T12	1		T13	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T226	1		T147	1		T227	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T43	6		T225	7		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	6		T53	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T205	1		T182	1		T146	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T166	18		T148	11		T228	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T129	3		T131	1		T229	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T46	1		T150	4		T62	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	1		T230	14		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T13	4		T15	12		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T46	5		T53	1		T141	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T152	15		T205	1		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T17	1		T128	1		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T9	1		T18	2		T20	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T175	1		T232	2		T233	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T19	3		T143	7		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T61	20		T53	1		T234	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T14	13		T40	5		T47	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T16	1		T150	13		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T62	11		T131	14		T156	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T15	13		T150	16		T225	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13603	1			T2	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T226	9		T157	9		T235	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T43	2		T225	7		T222	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T5	1		T53	6		T26	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T205	3		T146	19		T237	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T166	14		T148	8		T228	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T229	8		T177	1		T233	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T46	2		T62	1		T27	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T251	18		T252	2		T238	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	1		T145	11		T252	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T53	9		T153	11		T98	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T152	17		T231	10		T239	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T17	8		T154	9		T198	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1152	1			T18	14		T45	16		T93	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T175	10		T233	3		T241	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T19	1		T143	10		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T61	19		T53	7		T156	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T14	11		T40	1		T47	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T142	4		T254	13		T228	29
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T62	8		T156	7		T255	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T225	17		T256	16		T257	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T222	5		T104	8		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T184	1		T221	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T222	1		T224	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T222	1		T223	1		T242	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T227	2		T157	3		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T225	7		T164	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	6		T53	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T43	6		T182	1		T237	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T166	18		T244	1		T245	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T129	3		T205	1		T146	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T46	1		T150	4		T167	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T229	3		T246	1		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	12		T62	2		T152	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	1		T53	1		T141	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T13	4		T205	1		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T128	1		T46	5		T153	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T129	12		T144	1		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T17	1		T175	1		T232	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1452	1			T9	1		T18	2		T19	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T61	6		T234	13		T149	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	418	1			T14	13		T40	5		T47	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T15	13		T16	1		T61	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13601	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T221	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T222	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T222	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T157	9		T198	9		T258	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T225	7		T259	13		T248	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	1		T53	6		T226	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T43	2		T237	17		T197	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T166	14		T244	10		T180	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T205	3		T146	19		T177	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T46	2		T148	8		T158	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T229	8		T260	1		T256	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T62	1		T152	17		T145	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T53	9		T251	18		T252	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	1		T231	10		T239	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T153	11		T98	11		T154	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T250	10		T156	3		T149	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T17	8		T175	10		T156	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T18	14		T19	1		T45	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T61	5		T233	3		T160	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T14	11		T40	1		T47	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T61	14		T53	7		T142	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

auto[0]

4060

1

T5

1

T13

1

T14

11

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22473

1

T2

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19145

1

T2

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3328

1

T13

5

T14

24

T15

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16611

1

T2

20

T3

14

T4

20

auto[1]

5862

1

T9

1

T14

24

T15

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18523

1

T2

20

T3

14

T4

20

auto[1]

3950

1

T5

2

T9

2

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T131	1		T261	11		-	-
values[0]	76	1			T142	20		T37	1		T262	30
values[1]	610	1			T61	28		T144	1		T42	1
values[2]	630	1			T46	8		T205	4		T26	5
values[3]	614	1			T16	1		T47	25		T263	1
values[4]	733	1			T15	12		T19	4		T264	1
values[5]	2915	1			T9	1		T18	16		T20	17
values[6]	742	1			T5	7		T129	12		T61	11
values[7]	747	1			T13	5		T17	9		T40	6
values[8]	622	1			T12	1		T15	13		T128	1
values[9]	1171	1			T14	24		T129	3		T53	8
minimum	13601	1			T2	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	875	1			T46	8		T61	28		T144	1
values[1]	621	1			T16	1		T205	4		T94	11
values[2]	644	1			T15	12		T19	4		T47	25
values[3]	2938	1			T18	16		T20	17		T38	2
values[4]	661	1			T9	1		T129	12		T144	1
values[5]	724	1			T5	7		T61	11		T53	7
values[6]	748	1			T13	5		T17	9		T40	6
values[7]	684	1			T12	1		T14	24		T15	13
values[8]	769	1			T129	3		T53	10		T150	13
values[9]	208	1			T53	8		T225	2		T131	1
minimum	13601	1			T2	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

4060

1

T5

1

T13

1

T14

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T46	4		T62	2		T205	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T61	15		T144	1		T42	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T205	4		T26	4		T170	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T16	1		T94	1		T27	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T15	1		T19	3		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T47	13		T152	18		T263	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1522	1			T18	16		T20	2		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T264	1		T263	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	1		T129	1		T62	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T144	1		T230	1		T231	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T5	5		T61	6		T53	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T144	1		T25	1		T176	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T40	4		T150	1		T166	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	4		T17	9		T145	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	1		T150	1		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	12		T15	1		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T129	1		T53	10		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T150	1		T141	1		T62	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T225	1		T131	1		T265	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T53	8		T157	9		T194	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13485	1			T2	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T46	4		T62	1		T142	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T61	13		T95	8		T225	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T26	1		T248	7		T201	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T94	10		T27	1		T167	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	11		T19	1		T149	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T47	12		T152	14		T236	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1110	1			T20	15		T39	14		T139	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T131	2		T238	7		T266	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T129	11		T62	10		T43	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T230	13		T232	1		T134	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	2		T61	5		T98	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T167	7		T201	9		T240	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T40	2		T150	15		T166	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T13	1		T254	11		T267	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T150	3		T167	11		T246	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	12		T15	12		T225	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T129	2		T250	11		T156	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T150	12		T141	16		T62	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T225	1		T265	12		T86	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T157	7		T194	12		T268	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	2		T12	1		T13	3