Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22473

1

T2

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19155

1

T2

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3318

1

T5

7

T12

1

T14

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16696

1

T2

20

T3

14

T4

20

auto[1]

5777

1

T5

7

T9

1

T12

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18523

1

T2

20

T3

14

T4

20

auto[1]

3950

1

T5

2

T9

2

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	347	1			T14	24		T62	23		T232	2
values[0]	48	1			T311	25		T286	13		T325	10
values[1]	588	1			T9	1		T46	5		T129	3
values[2]	3122	1			T12	1		T16	1		T18	16
values[3]	501	1			T141	17		T205	4		T167	18
values[4]	586	1			T5	7		T144	1		T145	12
values[5]	650	1			T15	12		T128	1		T40	6
values[6]	711	1			T150	16		T144	1		T153	23
values[7]	703	1			T13	5		T61	39		T53	8
values[8]	564	1			T47	25		T150	4		T42	1
values[9]	1052	1			T15	13		T17	9		T53	10
minimum	13601	1			T2	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	513	1			T9	1		T12	1		T53	7
values[1]	3139	1			T16	1		T18	16		T19	4
values[2]	566	1			T205	4		T167	6		T222	6
values[3]	580	1			T5	7		T15	12		T144	2
values[4]	573	1			T128	1		T40	6		T129	12
values[5]	676	1			T150	16		T144	1		T153	23
values[6]	727	1			T13	5		T47	25		T61	39
values[7]	561	1			T150	4		T42	1		T94	12
values[8]	1119	1			T14	24		T15	13		T17	9
values[9]	149	1			T62	23		T96	8		T166	32
minimum	13870	1			T2	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

4060

1

T5

1

T13

1

T14

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	1		T53	7		T225	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	1		T226	10		T177	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1576	1			T16	1		T18	16		T19	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T176	12		T142	5		T225	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T205	4		T167	1		T252	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T222	6		T131	1		T252	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	1		T145	12		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	5		T144	2		T154	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T129	1		T150	1		T152	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T128	1		T40	4		T43	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T150	1		T144	1		T153	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T231	11		T252	3		T29	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	4		T47	13		T53	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T61	21		T222	16		T282	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T150	1		T94	2		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T42	1		T164	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T15	1		T62	9		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T14	12		T17	9		T53	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T96	8		T166	15		T198	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T62	13		T133	1		T134	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13567	1			T2	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T264	1		T196	1		T238	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T225	1		T197	8		T228	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T177	9		T233	4		T254	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1102	1			T19	1		T20	15		T39	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T142	15		T225	19		T167	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T167	5		T236	2		T30	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T131	2		T250	1		T235	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T15	11		T255	10		T239	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T5	2		T131	13		T194	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T129	11		T150	12		T152	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T40	2		T43	2		T250	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T150	15		T153	11		T26	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T29	1		T156	11		T227	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	1		T47	12		T62	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T61	18		T237	10		T159	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T150	3		T94	10		T143	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T148	10		T234	12		T239	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T15	12		T62	10		T232	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	12		T230	13		T146	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T166	17		T198	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T62	10		T134	12		T312	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T9	2		T12	1		T13	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T196	11		T238	7		T183	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T232	1		T229	9		T198	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T14	12		T62	13		T146	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T311	13		T286	11		T325	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	1		T46	1		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T264	1		T226	10		T177	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1615	1			T16	1		T18	16		T19	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T12	1		T176	12		T142	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T141	1		T205	4		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T167	1		T222	6		T252	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T145	12		T133	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	5		T144	1		T154	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T15	1		T129	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T128	1		T40	4		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T150	1		T144	1		T153	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T43	6		T231	11		T29	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	4		T53	8		T175	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T61	21		T222	16		T282	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T47	13		T150	1		T62	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T42	1		T131	1		T148	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T15	1		T62	9		T96	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T17	9		T53	10		T230	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13485	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T232	1		T229	2		T198	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T14	12		T62	10		T146	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T311	12		T286	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T46	4		T129	2		T225	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T177	9		T196	11		T238	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1100	1			T19	1		T20	15		T39	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T142	15		T225	19		T273	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T141	16		T167	5		T236	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T167	11		T250	1		T235	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T30	1		T239	1		T158	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	2		T131	2		T194	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T15	11		T129	11		T150	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T40	2		T131	13		T250	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T150	15		T153	11		T26	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T43	2		T29	1		T246	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	1		T134	10		T237	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T61	18		T156	11		T227	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T47	12		T150	3		T62	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T148	10		T248	13		T276	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T15	12		T62	10		T27	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T230	13		T134	12		T234	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	2		T12	1		T13	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T9	1		T53	1		T225	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T12	1		T226	1		T177	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1445	1			T16	1		T18	2		T19	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T176	1		T142	16		T225	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T205	1		T167	6		T252	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T222	1		T131	3		T252	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	12		T145	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	6		T144	2		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T129	12		T150	13		T152	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T128	1		T40	5		T43	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T150	16		T144	1		T153	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T231	1		T252	1		T29	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T13	4		T47	13		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T61	20		T222	1		T282	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T150	4		T94	12		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T42	1		T164	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T15	13		T62	11		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T14	13		T17	1		T53	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T96	1		T166	18		T198	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T62	11		T133	1		T134	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13705	1			T2	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T264	1		T196	12		T238	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T53	6		T251	18		T197	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T226	9		T177	1		T233	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T18	14		T19	1		T45	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T176	11		T142	4		T225	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T205	3		T252	12		T158	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T222	5		T252	11		T235	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T145	11		T255	14		T294	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T5	1		T154	9		T238	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T152	17		T273	12		T259	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T40	1		T43	2		T154	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T153	11		T26	1		T225	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T231	10		T252	2		T156	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	1		T47	12		T53	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T61	19		T222	15		T237	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T143	10		T178	4		T258	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T148	8		T239	2		T248	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T62	8		T27	1		T229	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T14	11		T17	8		T53	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T96	7		T166	14		T198	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T62	12		T300	9		T326	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T157	9		T238	6		T303	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T238	9		T183	14		T327	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T232	2		T229	3		T198	20
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T14	13		T62	11		T146	22
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T311	13		T286	3		T325	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	1		T46	5		T129	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T264	1		T226	1		T177	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1444	1			T16	1		T18	2		T19	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	1		T176	1		T142	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T141	17		T205	1		T167	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T167	12		T222	1		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T145	1		T133	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	6		T144	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T15	12		T129	12		T150	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T128	1		T40	5		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T150	16		T144	1		T153	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T43	6		T231	1		T29	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	4		T53	1		T175	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T61	20		T222	1		T282	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T47	13		T150	4		T62	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T42	1		T131	1		T148	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T15	13		T62	11		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T17	1		T53	1		T230	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13601	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T229	8		T198	11		T259	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T14	11		T62	12		T146	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T311	12		T286	10		T325	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T53	6		T157	9		T197	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T226	9		T177	1		T238	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T18	14		T19	1		T45	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T176	11		T142	4		T225	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T205	3		T252	12		T253	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T222	5		T252	11		T235	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T145	11		T158	4		T233	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	1		T154	9		T238	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T152	17		T255	14		T273	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T40	1		T154	6		T252	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T153	11		T26	1		T225	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T43	2		T231	10		T157	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	1		T53	7		T175	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T61	19		T222	15		T156	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T47	12		T62	1		T143	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T148	8		T248	13		T276	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T62	8		T96	7		T27	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T17	8		T53	9		T149	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

auto[0]

4060

1

T5

1

T13

1

T14

11