Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22473

1

T2

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18993

1

T2

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3480

1

T5

7

T12

1

T14

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16247

1

T2

20

T3

14

T4

20

auto[1]

6226

1

T5

7

T9

1

T17

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18523

1

T2

20

T3

14

T4

20

auto[1]

3950

1

T5

2

T9

2

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	378	1			T53	8		T41	1		T48	1
values[0]	104	1			T53	10		T95	17		T258	23
values[1]	593	1			T144	1		T62	19		T230	14
values[2]	2814	1			T18	16		T20	17		T38	2
values[3]	684	1			T5	7		T9	1		T16	1
values[4]	747	1			T12	1		T19	4		T47	25
values[5]	853	1			T15	12		T40	6		T129	3
values[6]	675	1			T14	24		T128	1		T61	28
values[7]	827	1			T61	11		T62	3		T175	11
values[8]	548	1			T46	3		T42	1		T98	23
values[9]	1006	1			T13	5		T15	13		T62	23
minimum	13244	1			T2	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	789	1			T53	17		T144	1		T62	19
values[1]	2850	1			T18	16		T20	17		T38	2
values[2]	687	1			T5	7		T9	1		T16	1
values[3]	849	1			T19	4		T150	13		T205	1
values[4]	747	1			T12	1		T14	24		T15	12
values[5]	806	1			T128	1		T205	4		T225	2
values[6]	616	1			T61	11		T42	1		T62	3
values[7]	552	1			T46	3		T175	11		T145	12
values[8]	708	1			T13	5		T15	13		T53	8
values[9]	245	1			T152	32		T170	1		T149	7
minimum	13624	1			T2	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

4060

1

T5

1

T13

1

T14

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T62	9		T230	1		T94	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T53	17		T144	1		T95	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1504	1			T18	16		T20	2		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T264	1		T247	1		T158	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T9	1		T16	1		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T5	5		T17	9		T47	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T205	1		T94	1		T222	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T19	3		T150	1		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T40	4		T43	6		T143	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T12	1		T14	12		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T128	1		T205	4		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T250	11		T134	1		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T62	2		T98	12		T154	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T61	6		T42	1		T153	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T46	3		T142	5		T225	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T175	11		T145	12		T252	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T13	4		T15	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T53	8		T62	13		T231	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T152	18		T170	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T237	13		T271	12		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13486	1			T2	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T299	1		T328	1		T329	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T62	10		T230	13		T250	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T95	8		T156	10		T268	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1054	1			T20	15		T39	14		T139	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T158	9		T238	7		T240	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T46	4		T129	11		T150	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T5	2		T47	12		T141	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T94	10		T239	1		T273	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T19	1		T150	12		T167	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T40	2		T43	2		T143	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T14	12		T15	11		T129	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T225	1		T166	17		T273	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T250	11		T134	12		T148	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T62	1		T98	11		T250	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T61	5		T153	11		T134	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T142	15		T225	19		T167	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T246	14		T273	5		T160	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T13	1		T15	12		T197	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T62	10		T232	1		T146	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T152	14		T149	6		T330	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T237	10		T271	14		T159	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	2		T12	1		T13	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T299	2		T328	5		T329	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	369	1			T41	1		T48	1		T49	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T53	8		T246	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T258	12		T297	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T53	10		T95	9		T187	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T62	9		T230	1		T94	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T144	1		T96	8		T182	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1531	1			T18	16		T20	2		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T53	7		T264	1		T282	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	1		T16	1		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T5	5		T17	9		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T205	1		T94	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	1		T19	3		T47	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T40	4		T143	11		T263	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T15	1		T129	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T128	1		T43	6		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	12		T61	15		T250	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T62	2		T205	4		T154	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T61	6		T175	11		T153	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T46	3		T98	12		T142	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T42	1		T131	1		T252	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	4		T15	1		T152	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T62	13		T231	11		T145	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13128	1			T2	20		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T258	11		T297	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T95	8		T187	2		T331	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T62	10		T230	13		T250	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T156	10		T238	7		T299	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T20	15		T39	14		T139	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T158	9		T159	13		T179	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T46	4		T129	11		T150	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T5	2		T26	1		T27	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T94	10		T239	1		T273	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T19	1		T47	12		T150	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T40	2		T143	6		T254	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T15	11		T129	2		T150	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T43	2		T225	1		T234	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	12		T61	13		T250	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T62	1		T166	17		T250	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T61	5		T153	11		T134	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T98	11		T142	15		T225	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T131	2		T273	5		T160	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	1		T15	12		T152	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T62	10		T232	1		T146	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	2		T12	1		T13	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T62	11		T230	14		T94	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T53	2		T144	1		T95	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T18	2		T20	17		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T264	1		T247	1		T158	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	1		T16	1		T46	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	6		T17	1		T47	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T205	1		T94	11		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T19	3		T150	13		T167	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T40	5		T43	6		T143	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	1		T14	13		T15	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T128	1		T205	1		T225	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T250	12		T134	13		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T62	2		T98	12		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T61	6		T42	1		T153	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T46	1		T142	16		T225	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T175	1		T145	1		T252	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	4		T15	13		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T53	1		T62	11		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T152	15		T170	1		T149	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T237	11		T271	15		T159	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13602	1			T2	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T299	3		T328	6		T329	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T62	8		T176	11		T296	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T53	15		T95	8		T96	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1161	1			T18	14		T45	16		T93	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T158	10		T238	9		T259	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T177	1		T156	7		T227	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T5	1		T17	8		T47	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T222	5		T273	14		T254	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T19	1		T235	1		T253	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T40	1		T43	2		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	11		T61	14		T226	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T205	3		T154	6		T166	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T250	10		T148	8		T158	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T62	1		T98	11		T154	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T61	5		T153	11		T252	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T46	2		T142	4		T225	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T175	10		T145	11		T252	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T13	1		T197	8		T198	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T53	7		T62	12		T231	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T152	17		T104	10		T330	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T237	12		T271	11		T332	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T310	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T41	1		T48	1		T49	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T53	1		T246	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T258	12		T297	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T53	1		T95	9		T187	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T62	11		T230	14		T94	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T144	1		T96	1		T182	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T18	2		T20	17		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T53	1		T264	1		T282	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T9	1		T16	1		T46	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T5	6		T17	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T205	1		T94	11		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	1		T19	3		T47	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T40	5		T143	7		T263	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T15	12		T129	3		T150	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T128	1		T43	6		T225	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	13		T61	14		T250	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T62	2		T205	1		T154	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T61	6		T175	1		T153	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T46	1		T98	12		T142	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T42	1		T131	3		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	4		T15	13		T152	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T62	11		T231	1		T145	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13244	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T104	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T53	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T258	11		T297	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T53	9		T95	8		T187	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T62	8		T233	15		T248	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T96	7		T251	18		T156	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T18	14		T45	16		T93	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T53	6		T158	10		T319	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T156	7		T227	19		T157	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	1		T17	8		T26	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T273	14		T253	15		T261	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T19	1		T47	12		T253	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T40	1		T143	10		T222	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T226	9		T225	7		T235	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T43	2		T239	3		T178	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	11		T61	14		T250	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T62	1		T205	3		T154	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T61	5		T175	10		T153	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T46	2		T98	11		T142	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T252	11		T273	10		T276	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T13	1		T152	17		T197	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T62	12		T231	10		T145	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

auto[0]

4060

1

T5

1

T13

1

T14

11