Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22473

1

T2

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19107

1

T2

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3366

1

T9

1

T12

1

T16

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16645

1

T2

20

T3

14

T4

20

auto[1]

5828

1

T5

7

T9

1

T13

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18523

1

T2

20

T3

14

T4

20

auto[1]

3950

1

T5

2

T9

2

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	363	1			T16	1		T40	6		T150	13
values[0]	15	1			T222	6		T223	1		T333	1
values[1]	555	1			T226	10		T225	14		T164	1
values[2]	582	1			T5	7		T53	7		T144	1
values[3]	641	1			T129	3		T205	4		T26	5
values[4]	571	1			T46	3		T150	4		T230	14
values[5]	736	1			T12	1		T15	12		T53	10
values[6]	792	1			T13	5		T17	9		T128	1
values[7]	565	1			T9	1		T129	12		T144	1
values[8]	2970	1			T18	16		T19	4		T20	17
values[9]	1082	1			T14	24		T15	13		T47	25
minimum	13601	1			T2	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	563	1			T43	8		T226	10		T164	1
values[1]	508	1			T5	7		T53	7		T144	1
values[2]	711	1			T129	3		T26	5		T146	41
values[3]	551	1			T12	1		T46	3		T150	4
values[4]	896	1			T13	5		T15	12		T46	5
values[5]	660	1			T17	9		T128	1		T152	32
values[6]	2836	1			T9	1		T18	16		T20	17
values[7]	609	1			T19	4		T61	39		T53	8
values[8]	1216	1			T14	24		T16	1		T40	6
values[9]	116	1			T15	13		T62	19		T255	25
minimum	13807	1			T2	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

4060

1

T5

1

T13

1

T14

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T226	10		T147	1		T227	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T43	6		T164	1		T222	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T5	5		T53	7		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T205	4		T131	1		T236	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T26	4		T166	15		T177	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T129	1		T146	20		T229	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T46	3		T150	1		T62	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	1		T230	1		T251	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	4		T15	1		T145	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T46	1		T53	10		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T152	18		T205	1		T231	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T17	9		T128	1		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T18	16		T20	2		T38	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T9	1		T175	11		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T19	3		T143	11		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T61	21		T53	8		T94	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	388	1			T14	12		T40	4		T47	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T16	1		T150	2		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T15	1		T62	9		T255	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T334	1		T256	17		T283	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13553	1			T2	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T225	8		T136	1		T223	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T227	1		T235	1		T271	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T43	2		T197	8		T254	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T5	2		T29	1		T194	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T236	2		T237	15		T273	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T26	1		T166	17		T177	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T129	2		T146	21		T229	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T150	3		T62	1		T27	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T230	13		T158	9		T196	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	1		T15	11		T225	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T46	4		T141	16		T153	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T152	14		T167	11		T239	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T167	7		T198	14		T240	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T20	15		T39	14		T129	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T232	1		T156	10		T233	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T19	1		T143	6		T131	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T61	18		T142	15		T234	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T14	12		T40	2		T47	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T150	27		T225	19		T134	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T15	12		T62	10		T255	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T256	12		T283	2		T280	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	2		T12	1		T13	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T225	6		T136	12		T248	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T40	4		T62	9		T164	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T16	1		T150	1		T334	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T222	6		T333	1		T335	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T223	1		T242	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T226	10		T227	1		T157	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T225	8		T164	1		T222	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	5		T53	7		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T43	6		T237	18		T254	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T26	4		T166	15		T177	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T129	1		T205	4		T146	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T46	3		T150	1		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T230	1		T229	9		T246	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	1		T62	2		T145	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	1		T53	10		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T13	4		T152	18		T205	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T17	9		T128	1		T46	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T129	1		T144	1		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T9	1		T175	11		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1551	1			T18	16		T19	3		T20	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T61	21		T234	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T14	12		T15	1		T47	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T53	8		T150	1		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13485	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T40	2		T62	10		T255	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T150	12		T228	16		T183	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T335	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T227	1		T157	2		T198	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T225	6		T136	12		T197	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T5	2		T29	1		T235	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T43	2		T237	15		T254	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T26	1		T166	17		T177	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T129	2		T146	21		T236	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T150	3		T167	5		T246	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T230	13		T229	2		T196	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T15	11		T62	1		T27	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T141	16		T94	10		T158	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T13	1		T152	14		T225	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T46	4		T153	11		T98	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T129	11		T250	11		T156	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T232	1		T167	7		T156	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1091	1			T19	1		T20	15		T39	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T61	18		T234	12		T149	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T14	12		T15	12		T47	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T150	15		T142	15		T225	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	2		T12	1		T13	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T226	1		T147	1		T227	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T43	6		T164	1		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T5	6		T53	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T205	1		T131	1		T236	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T26	4		T166	18		T177	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T129	3		T146	22		T229	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T46	1		T150	4		T62	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	1		T230	14		T251	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T13	4		T15	12		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T46	5		T53	1		T141	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T152	15		T205	1		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T17	1		T128	1		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T18	2		T20	17		T38	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	1		T175	1		T232	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T19	3		T143	7		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T61	20		T53	1		T94	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	394	1			T14	13		T40	5		T47	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T16	1		T150	29		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T15	13		T62	11		T255	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T334	1		T256	13		T283	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13656	1			T2	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T225	7		T136	13		T223	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T226	9		T235	1		T271	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T43	2		T222	15		T197	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T5	1		T53	6		T244	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T205	3		T237	17		T273	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T26	1		T166	14		T177	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T146	19		T229	8		T233	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T46	2		T62	1		T27	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T251	18		T252	2		T158	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	1		T145	11		T252	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T53	9		T153	11		T98	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T152	17		T231	10		T239	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T17	8		T154	9		T198	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T18	14		T45	16		T93	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T175	10		T156	8		T233	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T19	1		T143	10		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T61	19		T53	7		T142	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T14	11		T40	1		T47	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T225	17		T238	9		T254	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T62	8		T255	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T256	16		T336	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T222	5		T157	9		T183	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T225	7		T248	9		T311	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T40	5		T62	11		T164	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T16	1		T150	13		T334	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T222	1		T333	1		T335	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T223	1		T242	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T226	1		T227	2		T157	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T225	7		T164	1		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	6		T53	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T43	6		T237	16		T254	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T26	4		T166	18		T177	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T129	3		T205	1		T146	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T46	1		T150	4		T167	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T230	14		T229	3		T246	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T15	12		T62	2		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	1		T53	1		T141	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T13	4		T152	15		T205	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T17	1		T128	1		T46	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T129	12		T144	1		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T9	1		T175	1		T232	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1438	1			T18	2		T19	3		T20	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T61	20		T234	13		T149	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T14	13		T15	13		T47	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T53	1		T150	16		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13601	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T40	1		T62	8		T255	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T228	17		T183	12		T284	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T222	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T226	9		T157	9		T198	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T225	7		T222	15		T197	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	1		T53	6		T235	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T43	2		T237	17		T254	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T26	1		T166	14		T177	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T205	3		T146	19		T273	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T46	2		T148	8		T158	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T229	8		T260	1		T256	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T62	1		T145	11		T27	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T53	9		T251	18		T252	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	1		T152	17		T231	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T17	8		T153	11		T98	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T250	10		T156	3		T149	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T175	10		T156	8		T241	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T18	14		T19	1		T45	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T61	19		T233	3		T160	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T14	11		T47	12		T62	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T53	7		T142	4		T225	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

auto[0]

4060

1

T5

1

T13

1

T14

11