Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22473

1

T2

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18701

1

T2

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3772

1

T5

7

T9

1

T13

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16489

1

T2

20

T3

14

T4

20

auto[1]

5984

1

T12

1

T13

5

T14

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18523

1

T2

20

T3

14

T4

20

auto[1]

3950

1

T5

2

T9

2

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	296	1			T14	24		T141	17		T227	34
values[0]	29	1			T223	1		T297	26		T90	1
values[1]	572	1			T40	6		T129	3		T144	1
values[2]	608	1			T46	5		T53	7		T150	13
values[3]	474	1			T12	1		T15	12		T61	28
values[4]	937	1			T129	12		T47	25		T226	10
values[5]	2980	1			T15	13		T16	1		T18	16
values[6]	549	1			T205	4		T95	17		T25	1
values[7]	786	1			T9	1		T150	16		T42	1
values[8]	710	1			T5	7		T17	9		T53	18
values[9]	931	1			T13	5		T19	4		T128	1
minimum	13601	1			T2	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	545	1			T40	6		T46	5		T129	3
values[1]	567	1			T61	28		T53	7		T150	13
values[2]	577	1			T12	1		T15	12		T94	11
values[3]	3266	1			T16	1		T18	16		T20	17
values[4]	630	1			T15	13		T61	11		T205	4
values[5]	598	1			T42	1		T62	19		T95	17
values[6]	703	1			T9	1		T150	16		T62	23
values[7]	749	1			T5	7		T13	5		T17	9
values[8]	904	1			T14	24		T19	4		T46	3
values[9]	144	1			T141	17		T62	3		T233	10
minimum	13790	1			T2	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

4060

1

T5

1

T13

1

T14

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T40	4		T46	1		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T230	1		T26	4		T154	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T264	1		T166	15		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T61	15		T53	7		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T12	1		T182	1		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T15	1		T94	1		T226	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1593	1			T16	1		T18	16		T20	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T47	13		T145	12		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T15	1		T25	1		T225	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T61	6		T205	4		T142	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T42	1		T62	9		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T95	9		T263	1		T246	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T62	13		T177	2		T30	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T9	1		T150	1		T152	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T17	9		T128	1		T53	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	5		T13	4		T53	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T205	1		T232	1		T225	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T14	12		T19	3		T46	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T62	2		T233	4		T311	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T141	1		T337	1		T338	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13529	1			T2	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T238	10		T297	15		T339	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T40	2		T46	4		T129	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T230	13		T26	1		T156	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T166	17		T250	12		T134	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T61	13		T150	12		T153	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T253	12		T266	1		T279	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T15	11		T94	10		T233	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1098	1			T20	15		T39	14		T129	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T47	12		T149	11		T237	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T15	12		T225	19		T194	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T61	5		T142	15		T235	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T62	10		T131	2		T29	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T95	8		T236	2		T276	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T62	10		T177	9		T30	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T150	15		T152	14		T148	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T167	11		T149	6		T239	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	2		T13	1		T150	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T232	1		T225	6		T27	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T14	12		T19	1		T43	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T62	1		T233	6		T311	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T141	16		T337	1		T338	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	2		T12	1		T13	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T238	7		T297	11		T339	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T255	15		T237	18		T260	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T14	12		T141	1		T227	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T223	1		T90	1		T340	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T297	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T40	4		T129	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T230	1		T154	10		T156	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T46	1		T264	1		T166	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T53	7		T150	1		T153	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	1		T182	1		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T15	1		T61	15		T94	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T129	1		T146	20		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T47	13		T226	10		T145	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1531	1			T15	1		T16	1		T18	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T61	6		T176	12		T142	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T25	1		T225	18		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T205	4		T95	9		T246	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T42	1		T62	9		T177	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T9	1		T150	1		T152	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T17	9		T53	8		T62	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	5		T53	10		T231	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T128	1		T62	2		T205	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T13	4		T19	3		T46	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13485	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T255	10		T237	15		T260	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T14	12		T141	16		T227	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T297	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T40	2		T129	2		T167	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T230	13		T156	10		T227	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T46	4		T166	17		T229	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T150	12		T153	11		T26	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T253	12		T266	1		T279	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T15	11		T61	13		T94	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T129	11		T146	21		T225	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T47	12		T149	11		T271	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1077	1			T15	12		T20	15		T39	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T61	5		T142	15		T237	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T225	19		T131	2		T228	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T95	8		T236	2		T312	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T62	10		T177	9		T29	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T150	15		T152	14		T273	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T62	10		T167	11		T30	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T5	2		T143	6		T148	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T62	1		T232	1		T225	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T13	1		T19	1		T150	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	2		T12	1		T13	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T40	5		T46	5		T129	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T230	14		T26	4		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T264	1		T166	18		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T61	14		T53	1		T150	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T12	1		T182	1		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T15	12		T94	11		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1441	1			T16	1		T18	2		T20	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T47	13		T145	1		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T15	13		T25	1		T225	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T61	6		T205	1		T142	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T42	1		T62	11		T131	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T95	9		T263	1		T246	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T62	11		T177	10		T30	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	1		T150	16		T152	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T17	1		T128	1		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	6		T13	4		T53	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T205	1		T232	2		T225	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T14	13		T19	3		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T62	2		T233	7		T311	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T141	17		T337	2		T338	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13683	1			T2	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T238	8		T297	12		T339	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T40	1		T175	10		T229	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T26	1		T154	9		T156	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T166	14		T250	10		T157	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T61	14		T53	6		T153	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T252	2		T253	13		T279	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T226	9		T233	15		T180	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T18	14		T45	16		T93	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T47	12		T145	11		T176	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T225	17		T178	4		T228	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T61	5		T205	3		T142	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T62	8		T197	8		T254	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T95	8		T259	13		T276	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T62	12		T177	1		T239	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T152	17		T96	7		T231	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T17	8		T53	7		T154	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	1		T13	1		T53	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T225	7		T27	1		T250	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T14	11		T19	1		T46	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T62	1		T233	3		T311	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T338	13		T327	7		T341	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T156	7		T307	10		T342	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T238	9		T297	14		T316	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T255	11		T237	16		T260	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T14	13		T141	17		T227	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T223	1		T90	1		T340	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T297	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T40	5		T129	3		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T230	14		T154	1		T156	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T46	5		T264	1		T166	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T53	1		T150	13		T153	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T12	1		T182	1		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T15	12		T61	14		T94	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T129	12		T146	22		T225	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T47	13		T226	1		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1416	1			T15	13		T16	1		T18	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T61	6		T176	1		T142	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T25	1		T225	20		T131	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T205	1		T95	9		T246	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T42	1		T62	11		T177	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	1		T150	16		T152	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T17	1		T53	1		T62	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	6		T53	1		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T128	1		T62	2		T205	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T13	4		T19	3		T46	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13601	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T255	14		T237	17		T260	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T14	11		T227	19		T294	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T297	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T40	1		T175	10		T252	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T154	9		T156	8		T238	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T166	14		T229	8		T250	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T53	6		T153	11		T26	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T252	2		T253	13		T279	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T61	14		T233	15		T180	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T146	19		T238	6		T244	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T47	12		T226	9		T145	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1192	1			T18	14		T45	16		T93	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T61	5		T176	11		T142	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T225	17		T228	17		T256	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T205	3		T95	8		T276	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T62	8		T177	1		T239	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T152	17		T96	7		T252	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T17	8		T53	7		T62	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	1		T53	9		T231	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T62	1		T225	7		T154	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T13	1		T19	1		T46	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

auto[0]

4060

1

T5

1

T13

1

T14

11