Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22473

1

T2

20

T3

14

T4

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

16905

1

T2

20

T3

14

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

5568

1

T5

7

T9

1

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16520

1

T2

20

T3

14

T4

20

auto[1]

5953

1

T5

7

T9

1

T12

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18523

1

T2

20

T3

14

T4

20

auto[1]

3950

1

T5

2

T9

2

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	230	1			T46	5		T94	11		T96	8
values[0]	14	1			T16	1		T268	5		T343	8
values[1]	593	1			T5	7		T14	24		T154	10
values[2]	719	1			T40	6		T53	17		T42	1
values[3]	445	1			T17	9		T231	11		T131	1
values[4]	685	1			T15	12		T129	15		T150	16
values[5]	517	1			T46	3		T144	1		T62	3
values[6]	737	1			T12	1		T13	5		T15	13
values[7]	684	1			T150	4		T141	17		T144	2
values[8]	868	1			T175	11		T95	17		T226	10
values[9]	3380	1			T9	1		T18	16		T19	4
minimum	13601	1			T2	20		T3	14		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	615	1			T5	7		T42	1		T154	10
values[1]	3070	1			T17	9		T18	16		T20	17
values[2]	489	1			T231	11		T176	12		T131	1
values[3]	654	1			T15	12		T129	15		T150	16
values[4]	619	1			T12	1		T46	3		T61	28
values[5]	676	1			T13	5		T15	13		T47	25
values[6]	762	1			T150	4		T141	17		T144	2
values[7]	708	1			T62	23		T95	17		T225	2
values[8]	969	1			T9	1		T19	4		T128	1
values[9]	161	1			T96	8		T225	14		T252	13
minimum	13750	1			T2	20		T3	14		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

4060

1

T5

1

T13

1

T14

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T42	1		T164	1		T250	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	5		T154	10		T167	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T53	7		T158	16		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1665	1			T17	9		T18	16		T20	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T176	12		T131	1		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T231	11		T250	11		T156	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	1		T129	1		T205	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T129	1		T150	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T61	15		T62	2		T227	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	1		T46	3		T264	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	4		T15	1		T53	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T47	13		T61	6		T62	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T141	1		T144	2		T229	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T150	1		T175	11		T226	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T62	13		T225	1		T263	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T95	9		T263	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T46	1		T150	1		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T9	1		T19	3		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T96	8		T225	8		T177	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T252	13		T228	13		T344	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13520	1			T2	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T14	12		T16	1		T156	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T250	5		T236	2		T198	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T5	2		T167	7		T312	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T158	15		T159	13		T241	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1114	1			T20	15		T39	14		T40	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T233	5		T179	9		T283	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T250	11		T156	8		T271	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	11		T129	2		T98	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T129	11		T150	15		T156	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T61	13		T62	1		T227	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T131	13		T149	12		T273	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	1		T15	12		T29	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T47	12		T61	5		T62	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T141	16		T229	2		T250	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T150	3		T146	21		T143	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T62	10		T225	1		T167	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T95	8		T134	10		T276	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T46	4		T150	12		T234	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T19	1		T43	2		T94	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T225	6		T177	9		T235	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T228	12		T344	1		T345	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T9	2		T12	1		T13	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T14	12		T156	10		T268	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T46	1		T96	8		T225	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T94	1		T228	13		T240	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T343	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T16	1		T268	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T164	1		T250	21		T236	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	5		T14	12		T154	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T53	7		T42	1		T158	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T40	4		T53	10		T230	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T131	1		T233	17		T241	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T17	9		T231	11		T271	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T15	1		T129	1		T205	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T129	1		T150	1		T282	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T62	2		T94	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T46	3		T144	1		T264	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	4		T15	1		T61	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	1		T47	13		T61	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T141	1		T144	2		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T150	1		T62	9		T143	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T225	1		T263	1		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T175	11		T95	9		T226	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T150	1		T62	13		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1694	1			T9	1		T18	16		T19	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13485	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T46	4		T225	6		T177	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T94	10		T228	12		T240	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T268	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T250	5		T236	2		T198	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T5	2		T14	12		T167	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T158	15		T159	13		T346	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T40	2		T230	13		T131	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T233	5		T241	3		T283	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T271	14		T253	12		T299	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	11		T129	2		T98	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T129	11		T150	15		T250	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T62	1		T29	1		T227	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T149	6		T30	1		T157	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	1		T15	12		T61	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T47	12		T61	5		T152	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T141	16		T260	1		T267	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T150	3		T62	10		T143	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T225	1		T167	5		T229	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T95	8		T146	21		T276	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T150	12		T62	10		T227	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1179	1			T19	1		T20	15		T39	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	2		T12	1		T13	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T42	1		T164	1		T250	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	6		T154	1		T167	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T53	1		T158	17		T159	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1468	1			T17	1		T18	2		T20	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T176	1		T131	1		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T231	1		T250	12		T156	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T15	12		T129	3		T205	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T129	12		T150	16		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T61	14		T62	2		T227	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	1		T46	1		T264	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	4		T15	13		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T47	13		T61	6		T62	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T141	17		T144	2		T229	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T150	4		T175	1		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T62	11		T225	2		T263	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T95	9		T263	1		T134	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T46	5		T150	13		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T9	1		T19	3		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T96	1		T225	7		T177	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T252	1		T228	13		T344	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13622	1			T2	20		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T14	13		T16	1		T156	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T250	20		T198	2		T258	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	1		T154	9		T248	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T53	6		T158	14		T272	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1311	1			T17	8		T18	14		T45	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T176	11		T233	15		T284	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T231	10		T250	10		T156	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T205	3		T98	11		T142	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T156	3		T157	9		T238	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T61	14		T62	1		T254	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T46	2		T252	11		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T53	7		T145	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T47	12		T61	5		T62	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T229	8		T197	8		T279	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T175	10		T226	9		T146	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T62	12		T222	15		T251	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T95	8		T276	14		T203	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T149	12		T239	3		T296	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T19	1		T43	2		T26	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T96	7		T225	7		T177	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T252	12		T228	12		T344	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T256	12		T343	7		T185	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T14	11		T156	8		T268	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T46	5		T96	1		T225	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T94	11		T228	13		T240	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T343	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T16	1		T268	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T164	1		T250	6		T236	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	6		T14	13		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T53	1		T42	1		T158	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T40	5		T53	1		T230	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T131	1		T233	7		T241	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T17	1		T231	1		T271	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T15	12		T129	3		T205	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T129	12		T150	16		T282	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T62	2		T94	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T46	1		T144	1		T264	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	4		T15	13		T61	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	1		T47	13		T61	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T141	17		T144	2		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T150	4		T62	11		T143	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T225	2		T263	1		T167	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T175	1		T95	9		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T150	13		T62	11		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1553	1			T9	1		T18	2		T19	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13601	1			T2	20		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T96	7		T225	7		T177	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T228	12		T344	1		T345	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T343	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T268	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T250	20		T198	2		T258	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T5	1		T14	11		T154	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T53	6		T158	14		T272	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T40	1		T53	9		T253	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T233	15		T241	4		T284	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T17	8		T231	10		T271	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T205	3		T98	11		T176	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T250	10		T156	10		T238	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T62	1		T237	17		T160	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T46	2		T157	9		T273	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	1		T61	14		T53	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T47	12		T61	5		T152	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T260	1		T267	10		T274	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T62	8		T143	10		T254	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T222	15		T251	18		T229	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T175	10		T95	8		T226	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T62	12		T227	19		T239	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1320	1			T18	14		T19	1		T45	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18413

1

T2

20

T3

14

T4

20

auto[1]

auto[0]

4060

1

T5

1

T13

1

T14

11